This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.

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Implementing FFT-based digital channelized receivers on FPGA platforms

The problem of direction of arrival (DOA) estimation for multiple wideband sources using unattended passive acoustic sensors is considered. Several existing methods for narrowband DOA estimation are extended to resolve multiple closely spaced sources in presence of interference and wind noise. New wideband Capon beamforming methods are developed that use various algorithms for combining the power spectra at different frequency bins. A robust wideband Capon method is also studied to account for the inherent uncertainties in the array steering vector. Finally, to improve the resolution within an angular sector of interest and to provide robustness to sensor data loss, the beamspace method is extended and applied to the wideband problems. These methods are then tested and benchmarked on two real acoustic signature data sets that contain multiple ground vehicles moving in various formations.

Wideband DOA estimation algorithms for multiple moving sources using unattended acoustic sensors

This paper presents several implementations of digital channelised receivers on field-programmable gate array (FPGA) platforms for electronic warfare (EW) applications. All implementations are based on the fast Fourier transform (FFT) but they are intended for different applications. We have studied in detail and implemented different parallel architectures for the FFT algorithm in order to maximise speed processing and throughput, and to optimise area. On the other hand, monobit implementations of the FFT have been carried out in order to get real time in broadband digital receivers. Finally, in order to improve the detection of non-stationary signals, time-frequency analysis based on the short time Fourier transform (STFT) has also been implemented.

Digital channelised receivers on FPGAs platforms

A modular pipeline algorithm and architecture for computing discrete Fourier transforms is described. For an N point transform, two pipeline N point {square root}{square root over (N)} point fast Fourier transform modules are combined with a center element. The center element contains memories, multipliers and control logic. Compared with standard N point pipeline FFT, the modular pipeline FFT maintains the bandwidth existing pipeline FFTs with reduced dynamic power consumption and reduced complexity of the overall hardware pipeline.

Modular pipeline fast Fourier transform

Linear signal transforms (such as the discrete Fourier transform) are frequently used in digital signal processing and related fields. Algorithms for computing linear transforms are well-understood and typically have a high degree of regularity and parallelism, making them well-suited for implementation as sequential datapaths on field-programmable gate arrays or application-specific integrated circuits. Nonetheless, transforms are difficult to implement due to the large number of algorithmic options available and ways that algorithms can be mapped to sequential datapaths. Further, the best choices depend heavily on the resource budget and performance goals of the target application. Thus, it is difficult for a designer to determine which set of options will best meet a given set of requirements. This thesis proposes the Spiral hardware generation framework, a hardware compilation and optimization tool based on a mathematical formula language. A formula written in this language specifies a particular transform algorithm executed using a particular sequential datapath. This language allows high-level representation of sequential hardware structures that reuse datapath elements multiple times in the computation of a transform. The language accomplishes this by providing a formal connection between structure in the algorithm and sequential reuse in the datapath. This proposed language drives a hardware compilation system that takes as input a problem specification with directives that define characteristics of the desired datapath; the system then automatically generates an algorithm, maps the algorithm to a datapath, and outputs synthesizable register transfer level Verilog. This thesis evaluates the generated designs when synthesized for field-programmable gate array or application-specific integrated circuit. Its evaluations consider designs across multiple transforms, datatypes, and design goals, and its results show that Spiral is able to automatically provide

A mathematical approach for compiling and optimizing hardware implementation of DSP transforms

The fast Fourier transform (FFT) and its inverse (IFFT) are two of the most widely used building blocks in digital signal processing designs. A novel structure for a radix-4 type FFT is proposed which can process frames of 16-bit complex samples at a rate of one output sample per 100 MHz clock cycle, thus performing a 1024-point transform in approximately 10 /spl mu/s. The dedicated, parallel multiplier and distributed block memory features of the Virtex/sup /spl reg//-II FPGA family provide the designer with a single chip solution where external components such as memory are not required.

G. Szedo

Papers

High-performance FFT processing using reconfigurable logic