Built-in logic block observation techniques

A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.

Built-In Self-Test Techniques

A built-in test system employs dual-mode feedback shift registers to supply test vectors and evaluate test responses of functional and interface networks of a logic system. Test responses are supplied to a quotient bit compressor which generates a system response signature for comparison with an expected fault-free signature to produce a system pass/fail status signal.

G. W. K. Lee

Papers

Fault detection/isolation results from AAFIS hardware built-in-test