A power converter system comprises a switching power converter having a primary side and a secondary side that are electrically isolated from each other. A first controller on the primary side of the switching power converter controls a switch in the switching power converter on or off at a switching frequency of the switching power converter to regulate an output voltage of the switching power converter. A second controller on the secondary side of the switching power converter encodes information into one or more pulses such that a first duration between the consecutive pulses corresponds to a first logic level and a second duration between the consecutive pulses corresponds to a second logic level, the second duration being greater than the first duration.

Protocol for communication between secondary side and primary side of isolated switching power converters

The invention discloses a frequency shift keying (FSK) or a Gauss frequency shift keying (GFSK) digital demodulation device and method. The device comprises an FSK or GFSK demodulation circuit and a code element recovery circuit, wherein the FSK or GFSK demodulation circuit is used for detecting the intermediate frequency of a modulation signal so as to demodulate the modulation signal by adopting proper intermediate frequency, and outputting a demodulation result; and the code element recovery circuit is used for counting positions of a rising edge and a falling edge of the demodulated signal output by the FSK or GFSK demodulation circuit, searching for an initial position of a proper single code element and outputting an accurate code element. The FSK or GFSK digital demodulation device and the FSK or GFSK digital demodulation method have the advantages that: a bit error rate is low, and the parameter setting of a scheme is regulated according to different frequency shift tolerances so as to achieve simple structure and high flexibility; the code element can be effectively recovered and the offset of an external clock can be resisted; and only a digital circuit is adopted so as to achieve low cost.

Gauss) frequency shift keying ((G)FSK) digital demodulation device and method

A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic ‘0’ level of the FSK signal, and a third clock and fourth clock framing a logic ‘1’ level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic ‘0’ envelope, a logic ‘1’ envelope, a lower frequency envelope below the logic ‘0’ envelope, and an upper frequency envelope above the logic ‘1’ envelope. R'Edge is compared to the four envelopes, and a decoded output is produced, logic ‘0’ if the R'Edge overlaps the logic ‘0’ envelope, logic ‘1’ if R'Edge overlaps the logic ‘1’ envelope, and a previous output state if R'Edge does not overlap the logic ‘0’ or logic ‘1’ envelope.

FSK decoding using envelope comparison in the digital domain

This application discusses among other things, apparatus and method for transmitting data with an analog signal without significantly distorting the analog signal. In an example, an apparatus can include an audio channel, a capacitor coupled to a first conductor of the audio channel, the capacitor configured to couple an analog representation of a digital data signal with an analog audio signal on the audio channel, and a frequency modulator configured to receive the digital data signal and to modulate a frequency of an output signal of the frequency modulator based on a logic level of the digital data signal, wherein the analog representation of the digital data signal includes the frequency of the output signal of the frequency modulator.

Data during analog audio

A receiver performs independent packet detection using synchronization words with orthogonality when multiple signals on which frequency-shift keying is performed coexist. The receiver includes a frequency demodulator generating a quasi-amplitude modulation signal that has a value proportional to frequency shift from the first signal or second signal being received, a sign discriminator discriminating a sign of the generated quasi-amplitude modulation signal, and a multi-binary correlator calculating a first correlation value which is a binary correlation value between the discriminated sign and a first synchronization word and calculating a second correlation value which is a binary correlation value between the discriminated sign and a second synchronization word.

Independent packet detection method using synchronization words with orthogonality and receiver therefor

A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.

Configurable demodulator and demodulation method

A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation. The system for modulation-based commutations link includes a modulation unit having a dividing mechanism for dividing a reference clock by a divide value, and a configuration register for one or more configurable divide sequences.

Multi-format all-digital modulator and method

A method, system and digital modulator for modulation are provided. The modulator includes a dividing mechanism for dividing a reference clock by a divisor value to produce a modulated signal associated with input data, and a control unit for providing at least one divisor sequence to the dividing mechanism. The divisor sequence is configurable and depends on the input data.

Gareth P. Weale

Papers

Configurable demodulator and demodulation method

Multi-format all-digital modulator and method

Frequency modulation using division of a reference clock signal