Approximate computing is gaining grip as a computing paradigm for computer vision, data analytics, and image/signal processing applications. In the era of real-time applications, approximate computing plays a significant role. In many computers including digital signal processors (DSP) and a microprocessor, adders are the main element for the implementation of signal processing applications and digital circuit design. The major problem for addition is the propagation delay in the carry chain. As the bit length of the input operand increases, the length of the carry chain increases. To address the carry propagation problem in digital systems, the most efficient adder architectures for VLSI implementation are classified as a parallel prefix adder (PPA) structure. In this paper, a novel methodology to implement and synthesize different adders (non-speculative and speculative) for any ASIC-based system is proposed. The proposed hybrid Han-Carlson and Kogge-stone speculative adders show improved performance (low power and delay) over the state-of-the-art approximate adders. If the approximation fails, then the proposed efficient error correction technique is activated. The proposed speculative H_C adder results in a 23.79% speed improvement over the proposed K_S adder, and 23.86% of energy is saved. The proposed architectures were synthesized for an operand bit length of 16 bits. Finally, the proposed adder is validated for an error-tolerant image processing application resulting in 41.2 dB PSNR.

A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application

The Fast Fourier Transform (FFT) is the basic building block for DSP applications where high processing speed is the critical requirement. Resource utilization and the number of computational stages in Radix-2 FFT structure implementation can be minimized by improving the performance of utilized multiplier and adder blocks. This work proposes a hardware design of an efficient Radix-2 FFT architecture using optimized multiplier and novel Parallel prefix (PP) adder. The designed FFT architecture results in low power and area with an increase in operation speed in comparison to the existing architectures. Our proposed Radix 2 FFT implementation results in 18.218 ns (6.030 ns logic delay and 12.118 ns router delay) in comparison with 24.003 ns delay for Wallace multiplier using Kogge Stone PP adder (M1P1), 24.162 ns delay for Wallace multiplier using Brent Kung PP adder (M2P2), 24.889 ns delay for Wallace multiplier using Landner Fischer PP adder (M3P3) and 22.827 ns delay for Wallace multiplier using Han Carlson PP adder (M4P4) algorithm. The proposed adder and hence the FFT processor can be used in different applications where high speed, low power, and less area is required. The novel PP architecture results in a 20.19% improvement in comparison with other state-of-art techniques.

A novel parallel prefix adder for optimized Radix-2 FFT processor

Adders play a crucial role and are one of the fundamental building blocks in application like signal processing. In the modern scenario, integrated circuits are majorly used in which the requirement of adder module is vital. This paper addresses various forms of adders which include Ripple-carry (RC), Carry-skip (CSk), Carry-lookahead (CL) and Kogge-stone(KS) adders. These adders can meet certain design constraints in digital VLSI circuits, such as speed and area. For various bit-lengths, a new KS adder is proposed in this paper which was analyzed on the basis of delay. The proposed adder with 8, 16, 32, 64 and 128 bit-length results in 7.487ns, 9.248ns, 10.295ns, 7.259ns and 6.814ns delay respectively.84.11% improvement has been analyzed for 128 bit KS adder in comparison with CSk adder, 88.34 % in comparison with RC adder and 88.83% in comparison with CL adder. The proposed KS architecture can be used in time critical FPGA based signal processing applications.

Design and Analysis of High-Speed Parallel Prefix Adder for Digital Circuit Design Applications

Approximate computing provides the tradeoff between the accuracy, the speed as well as power consumption. Approximate adders and other logical circuits can reduce hardware overhead. In this paper non-speculative and speculative parallel prefix adder is proposed and makes it more reliable to be used in applications where high speed circuits are required. If there is misprediction of result in speculative adder then error-correction is activated in the next clock cycle. Speculation is a process in which approximation is done. Approximate computing is widely used in the current scenario. The speculative adder reduces the critical path and provides the trade-off between reliability and performance. Proposed speculative parallel prefix adder results in 8.204ns delay which shows 36.87%, 2.35%, 26.32 % improvement in comparison to conventional NSA, proposed NSA, and conventional SA. Architecture is implemented for 16-bit operand length and used is an FPGA-based processing application.

FPGA-Based Parallel Prefix Speculative Adder for Fast Computation Application

Nanoscale ICs required components with increased speed and less consumption of power. The trade-off between speed, area, and power is an important task. For the optimization of these parameters, approximate computing is used. In this paper, the approximate high-order compressor is implemented which is further used in partial product reduction of the multiplier. It is important to increase the computational parameters of the multiplication process. The performance of the multiplier increases by using compressors. In this paper, the authors proposed 9:2 compressor which helps in the reduction of the complexity of the circuit and increases the performance of the multiplication block. By applying compressors in the multiplication block, an energy-efficient multiplier is implemented. An energy-efficient multiplier can be further used in error-tolerant applications. The proposed approximated multiplier consumes 43.93% low power and area utilization 49.52 % less as compared to the exact multiplier. All the simulation is carried out in VIVADO 2018.3 using Verilog HDL coding.

Implementation of Approximate Multiplier using Inexact Compressors

In Signal Processing applications the arithmetic units mainly consists of adders and multipliers. These arithmetic units are used in to enhance the performance of Fast Fourier Transform (FFT) Butterfly structure implementation. This paper discusses the addition and multiplication algorithms for parameters like speed, area and power. The best suited among all adders are Kogge Stone Adder (KSA) while among multipliers are Wallace multiplier(WM) which is used for the implementation of the FFT structure. Verilog coding is used for implementation of circuit and the tool used is Xilinx ISE 14.1 Design suite. 

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Garima Thakur

Papers

A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application

A novel parallel prefix adder for optimized Radix-2 FFT processor

Design and Analysis of High-Speed Parallel Prefix Adder for Digital Circuit Design Applications

FPGA-Based Parallel Prefix Speculative Adder for Fast Computation Application

High Speed RADIX-2 Butterfly Structure Using Novel Wallace Multiplier