Showing papers by "Garrett S. Rose published in 2005"

An SRAD Image Processor as a Reconfigurable, Temperature-Aware SoC Designed for Low-Power Operation

Abstract: A SoC implementation of an ultrasound-imaging system is presented. Achieving higher performance, lower power consumption, greater reliability is the major goal of this design. In addition, a novel ultrasound image enhancement algorithm is first shown implemented in a SoC. The system has higher performance due to the fact of less communication latency and application-specific digital signal processing obtained by the system-on-chip approach. The design consumes lower power is mainly due to the implementation of Dynamic Voltage Scaling (DVS) based on the runtime DSP output—low power is achieved without sacrificing the quality and the speed of the output video stream. The system is more reliable is because Dynamic Thermal Management (DTM) techniques are implemented to prevent the system from potential thermal hazards and at the same time make the system less costly and more portable by using cheaper thermal package. Another factor that improves the reliability of the system is due to the reconfigurability feature, where faults and defects can be detected and reconfigured. Detailed design methodology is presented. Preliminary design, simulation results and testing plans are shown. The system has been implemented and tested on an FPGA prototype.