Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the data block, the input data stream comprising a plurality of disparate data types; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.

Content independent data compression method and system

An ASIC device embedded into the memory subsystem of a computing device used to accelerate the transfer of active memory pages for usage by the system CPU from either compressed memory cache buffer or the addition of a compressed disk subsystem for improved system cost and performance. The Compression Enhanced Dual In-line Memory Module of the present invention uses parallel lossless compression and decompression engines embedded into the ASIC device for improved system memory page density and I/O subsystem data bandwidth. In addition, the operating system software optimizes page transfers between compressed disk partitions, compressed cache memory and inactive/active page memory within the computer system. The disclosure also indicates preferred methods for initialization, recognition and operation of the ASIC device transparently within industry standard memory interfaces and subsystems. The system can interface to present operating system software and applications, which enable optimal usage for the compressed paging system memory environment. The integrated parallel data compression and decompression capabilities of the compactor ASIC mounted on industry standard memory modules, along with the software drivers and filters of the present invention keep recently used pages compressed in the system memory. Additional performance is gained by the transfer of compressed pages between the system memory and the disk and network subsystems. In addition, the present invention may reduce the amount of data transferred between distributed computers across the LAN or WAN by the transmission of compressed page data between remote systems or distributed databases.

Parallel compression/decompression system and method for implementation of in-memory compressed cache improving storage density and access speed for industry standard memory subsystems and in-line memory modules

A nonvolatile memory system emulates a magnetic hard disk drive and includes an array of nonvolatile memory cells, such as flash memory cells, organized into sets, such as sectors. A buffer, such as a random access memory, stores a first set of data to be written to the array. Error correction code (ECC) circuitry receives the first set of data and calculates first ECC check bits representative of the first set of data. ECC comparison circuitry compares the first ECC check bits with second ECC check bits representative of a second set of data stored in the array to generate an ECC comparison signal having a first state indicative of a match between the first and second ECC check bits and a second state indicative of a miscomparison between the first and second ECC check bits.

Write reduction in flash memory systems through ECC usage

A flash memory controller and/or embedded memory controller including MemoryF/X Technology that uses data compression and decompression for improved system cost and performance. The Compression Enhanced Flash Memory Controller (CEFMC) of the present invention preferably uses parallel lossless compression and decompression engines embedded into the flash memory controller unit for improved memory density and data bandwidth. In addition, the invention includes a Compression Enhanced Memory Controller (CEMC) where the parallel compression and decompression engines are introduced into the memory controller of the microprocessor unit. The Compression Enhanced Memory Controller (CEMC) invention improves system wide memory density and data bandwidth. The disclosure also indicates preferred methods for specific applications such as usage of the invention for solid-state disks, embedded memory and Systems on Chip (SOC) environments. The disclosure also indicates a novel memory control method for the execute in place (XIP) architectural model. The integrated parallel data compression and decompression capabilities of the CEFMC and CEMC inventions remove system bottle-necks and increase performance matching the data access speeds of the memory subsystem to that of the microprocessor. Thus, the invention allows lower cost systems due to smaller data storage, reduced bandwidth requirements, reduced power and noise.

Parallel decompression and compression system and method for improving storage density and access speed for non-volatile memory and embedded memory devices

Systems and methods for providing accelerated loading of operating system and application programs upon system boot or application launch are disclosed. In one aspect, a method for providing accelerated loading of an operating system comprises the steps of: maintaining a list of boot data used for booting a computer system; preloading the boot data upon initialization of the computer system; and servicing requests for boot data from the computer system using the preloaded boot data. In another aspect, a method for providing accelerated launching of an application program comprises the steps of: maintaining a list of application data associated with an application program; preloading the application data upon launching the application program; and servicing requests for application data from a computer system using the preloaded application data.

Systems and Methods for Accelerated Loading of Operating Systems and Application Programs

A data compression controller for processing data between a host system and at least one device is disclosed. The data compression controller comprises a compression coprocessor for converting data between first format and second format at a determined controller ratio. The compression has two buffers for storing data of the first and second formats. When data is to be compressed, the coprocessor receives data directly from the host system into the first buffer. The coprocessor reads the buffered data and compresses the data for output to the external device through the second buffer. A coprocessor interface is coupled to the coprocessor for monitoring the buffers to determine the state of the buffers and the coprocessor; for example, if the such that the data to be compressed flows smoothly and consistently through the coprocessor. The input/output (I/O) controller is coupled to the coprocessor and the device for transferring data between the second buffer and the device. The I/O controller interface monitors the state of the I/O controller and provides the necessary control signals to indicate when to begin the transfer of compressed data to the device. In addition, the I/O controller interface configures and controls the I/O controller according to the device. Therefore, a single An application interface is coupled to the host system, for decoding commands from the host system, and issuing corresponding signals to the components of the controller to execute the commands. The application interface monitors the status of the controller through the I/O controller interface and the coprocessor interface and provides status information to the host system such that the host timely provides data to the coprocessor and the necessary commands to the application interface to maintain continuous movement of data through the coprocessor.

Gary T. DalSanto

Papers

Data compression controller