Embodiments of the present invention include a method of depositing an improved seasoning film. In one embodiment the method includes, prior to performing a substrate processing operation, forming a layer of silicon over an interior surface of the substrate processing chamber as opposed to a layer of silicon oxide. In certain embodiments, the layer of silicon comprises at least 70% atomic silicon, is deposited from a high density silane (Si n H 2n+2 ) process gas and/or is deposited from a plasma having a density of at least 1×10 11 ions/cm 3 .

Si seasoning to reduce particles, extend clean frequency, block mobile ions and increase chamber throughput

An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

Isolation system with digital communication across a capacitive barrier

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.

Digital isolation system with ADC offset calibration

An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. A bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information. Finally, the isolation system may include a pulse transformer to accommodate ADSL circuitry, whereby power is transmitted through the pulse transformer.

Direct digital access arrangement circuitry and method for connecting DSL circuitry to phone lines

A telephone network interface integrated circuit with digitally based loop current detection and digitally based ring signal detection. The ring signal detection includes discrimination with a cutoff frequency of about 13 Hz to distinguish ring signals from dialing signals. The discrimination includes filtration followed by triggering an oscillator for one time period and checking whether the number of oscillations exceeds a threshold.

Ring signal detection circuit

An integrated circuit which, for ESD protection at an input pad, uses a split series resistor, with two clamping diodes of different types. By splitting up the series resistance in this fashion, some impedance is provided before the first hard diode, without causing an excessive total impedance. When a positive-going transient appears at the pad, the current is limited only by a moderate impedance (which saves area); when a negative-going transient appears, the current is limited by a much higher impedance (which allows a lower leakage current to be achieved).

ESD circuit for input which exceeds power supplies in normal operation

A class of layout patterns for variable resistors and integrated circuits where the resistance is varied by varying a wiping point on a resistor line; contact is not made into the resistor line itself, but instead all contacts are made only to tabs which extend out from the resistor line. Preferred embodiments use a meander resistor line made of polysilicon within a silicon integrated circuit. Simple processing mask modifications can be used to change the geometry of the meander line to vary the resistance. The wiping point is digitally selected.

Gary V. Zanders

Papers

Ring signal detection circuit

ESD circuit for input which exceeds power supplies in normal operation

Thin-film resistor layout