The invention discloses a high performance network tester and a testing method of the high performance network tester with the adoption of a FPGA+PowerPC+ARM framework. The network tester comprises a RJ45 interface, a transformer, a physical interface (PHY), an optical interface SFP, an FPGA, a PowerPC, an ARM and a display control device. The FPGA completes the generation and reception of testing flows, conducts analysis of a first layer message and a second layer message, controls the FPGA and surveys the first layer message and the second layer message; the PowerPC conducts analysis of a network protocol on a third layer or layers above; the ARM communicates with a computer to realize the display and control of entire equipment. According to the invention, the network tester puts together the advantages of three processors. The network tester is provided with high flexibility and is cost-effective to make. The tester is also compatible with a variety of interfaces and has strong expansibility.

High performance network tester and the testing method thereof

The invention discloses a digital phase position checking device by using an identical clock source for calibrating sampling time. The digital phase position checking device by using the identical clock source for calibrating the sampling time comprises an FPGA (field-programmable gate array) hardware unit used for front-end signal acquisition, a PowerPC microprocessor used for back-end data processing, an SDRAM (synchronous dynamic random access memory) and a FLASH, wherein the FPGA hardware unit is connected with the PowerPC microprocessor through a bus, and the SDRAM and the FLASH are connected with the bus. A synchronous pulse signal receiving interface, an A/D (analog/digital) sampling interface, two parallel FT3 data receiving interfaces and two parallel optical Ethernet data receiving interfaces are arranged at an input end of the FPGA hardware unit. The digital phase position checking device by using the identical clock source for calibrating the sampling time has the advantages of simple structure, convenience in manufacture and high practicality, phase position checking error caused by crystal oscillator error from different clock sources in the prior art can be eliminated, response consistency is guaranteed, and urgent demands of intelligent substations and digital substations on high precision of electrical quantity phase position checking can be satisfied.

Digital phase position checking device by using identical clock source for calibrating sampling time

The invention discloses a protocol converter for digitally calibrating a current transformer of a DC converter station. The protocol converter comprises a data acquisition and analysis module, a communication module, a POWERPC embedded processor, a TCP/IP protocol stack, and an external synchronization clock device. The external synchronization clock device is used for triggering a second pulse signal to the data acquisition and analysis module. The data acquisition and analysis module is used for receiving and analyzing an FT3 frame format optical signal. The data acquisition and analysis module is an FPGA which samples the FT3 frame format optical signal. The data acquisition and analysis module generates a corresponding timestamp when receiving the FT3 frame format optical signal, and sends the timestamp and data processed by the FPGA to the communication module. The data acquisition and analysis module is connected with the external synchronization clock device, and receives the second pulse signal triggered by the external synchronization clock device and carries out counting and time scale making synchronization.

Protocol converter for digitally calibrating current transformer of DC converter station

The utility model discloses a digital phase approval device utilizing the same clock source to calibrate sampling time. The device comprises an FPGA hardware unit used for front signal acquisition, and a PowerPC microprocessor used for back data processing that are connected with each other through a trunk. The device further comprises a SDRAM and an FLASH that are connected to the trunk. The input end of the FPGA hardware unit is provided with a synchronous pulse signal receiving interface, an A/D sampling interface, two parallel FT3 data receiving interfaces and two parallel fiber Ethernet data receiving interfaces. The device is advantaged by being simple in structure, convenient in making and high in practicality. The device eliminates phase calibration errors caused by crystal oscillator errors of different clock sources in the prior art, ensures response consistency, and then meets the urgent requirements of high precision of phase approval of electrical quantities in intelligent transformer stations and digitalized transformer stations.

Geng Zhendong

Papers

Digital phase position checking device by using identical clock source for calibrating sampling time

Digital phase approval device utilizing same clock source to calibrate sampling time