An electrosurgical system for sealing tissue is disclosed that includes an electrosurgical forceps. The forceps includes a drive rod and an end effector assembly coupled to the drive rod at a distal end thereof. The end effector assembly includes jaw members wherein longitudinal reciprocation of the drive rod moves the jaw members from a first position in spaced relation relative to one another to a subsequent position wherein the jaw members cooperate to grasp tissue therebetween. Each of the jaw members includes a sealing plate that communicates electrosurgical energy through tissue held therebetween. The jaw members are adapted to connect to an electrosurgical generator. The system also includes one or more sensors that determine a gap distance between the sealing plates of the jaw members and a pressure applicator coupled to the drive rod. The pressure applicator is configured to move the drive rod in a longitudinal direction. The system further includes a controller adapted to communicate with the sensors and to control the pressure applicator in response to the determined gap distance during the sealing process.

System and Method for Controlling Electrode Gap During Tissue Sealing

Design of the leading zero anticipator (LZA) or detector (LZD) is pivotal to the normalization of results for addition and fused multiplication-addition in high-performance floating point processors. This paper formalizes the analysis and describes some alternative organizations and implementations from the known art. It shows how choices made in the design are often dependent on the overall design of the addition unit, on how subtraction is handled when the exponents are the same, and on how it detects and corrects for the possible one-bit error of the LZA.

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Leading zero anticipation and detection-a comparison of methods

A floating point addition unit includes two subunits each of which performs the addition. One subunit ("rounding subunit") rounds the addition result, and the other subunit ("non-rounding subunit") does not. The result of the rounding subunit is selected as the addition result when one of the following conditions (R1), (R2), (R3) is true: (R1) the operation is an effective addition; (R2) the operation is an effective subtraction, the magnitude ED of the difference between the exponents of the operands is 1, and normalization of the result is not required; (R3) the operation is an effective subtraction and ED>1. The addition result is selected from the non-rounding subunit in the remaining cases. In some embodiments, the rounding subunit overlaps rounding with adding the operands, significands. In some embodiments, the addition unit satisfies ANSI/IEEE Standard 754-1985.

Floating point addition methods and apparatus

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

A method for designing a constant multiplier system comprises identifying a repeated pattern in a minimal signed digit expression of a multiplier, designing a first accumulator stage to compute the product of a multiplicand by an instance of the pattern, and designing a second accumulator stage for accumulating shifted replicas of the pattern to yield a final product. Remainder terms, for example corresponding to non-zero digit positions not included in any instance of the pattern, are also accumulated at the second stage. By limiting the method to patterns with at least two non-zero values, the result tends to reduce the number of operations that must be performed to determine a final product. Thus, the size, complexity and speed of a constant multiplier system can be optimized.

Method and apparatus for computer implemented constant multiplication with multipliers having repeated patterns including shifting of replicas and patterns having at least two digit positions with non-zero values

To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a master latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

Flip-flop circuit

A bit-discard amount anticipator anticipates a bit-discard amount within a one-bit error. A borrow propagator propagates a borrow from a least significant bit side. A selector modifies an output of the bit-discard amount anticipator to an accurate bit shift amount required at a normalization and outputs it, using information of the borrow propagator. The bit shift amount for the normalization in case where a bit discard is caused at a mantissa subtraction of a floating point calculation is accurately obtained, thus reducing a process at the normalization.

Leading one anticipator and floating point addition/subtraction apparatus

In the case of addition/subtraction of floating-point numbers, two mantissas having their digits aligned in a swapper and in a right shifter are supplied to an adder/subtracter via first and second mantissa selectors and two 1-bit right shifters so that they are subjected to addition/subtraction in the adder/subtracter, the result of which is rounded. In the case of multiplication/division of floating-point numbers, an intermediate sum and a carry, each outputted from a multiplier, are supplied to the above adder/subtracter via the above first and second mantissa selectors and the above two 1-bit right shifters, so that they are added in the adder/subtracter, the result of which is rounded. The result of rounding from the adder/subtracter is outputted as a normalized mantissa through a priority encoder and a left shifter. An exponent is processed by first to third exponent arithmetic units and an exponent selector. Thus, the amount of hardware of an arithmetic apparatus for executing the addition, subtraction, multiplication, and division of floating-point numbers can be reduced.

Arithmetic apparatus for floating point numbers

A test circuit according to the present invention performs a test of a first tri-state device and a second tri-state device having their outputs connected to the same node, and includes: a test output terminal; and a test unit operable to output a first logical value or a second logical value to the test output terminal according to whether the voltage of the node is higher or lower than a threshold value, and the test unit converts the intermediate potential occurring at the node into the first logical value and outputs the first logical value to the test output terminal when the first tri-state device outputs a high level signal to the node and the second tri-state device outputs a low level signal to the node.

Test circuit, selector, and semiconductor integrated circuit

The present invention discloses a multiplication device. A multiplicand X of eight bits and a multiplier Y of eight bits are input and a product P of sixteen bits is found from these multiplication factors. MULTIPLICAND X is divided into two parts, an upper-order part X U of four bits and a low-order part X L of four bits. MULTIPLIER Y is likewise divided into two parts, an upper-order part Y U of four bits and a low-order part Y L of four bits. Thereafter, four 8-bit partial products, i.e., X L ×Y L , X L ×Y U , X U ×Y L , and X U ×Y U are computed one after another. These partial products are subjected to a digit place alignment addition operation, by an adder, to compute PRODUCT P. Computation of each of the partial products is implemented by performing addition of an approximate partial product AP retrieved by a 6-bit address from a 64-byte ROM, and a correction value H and a carry C generated by a correction value generator.

Genichiro Inoue

Papers

Flip-flop circuit

Leading one anticipator and floating point addition/subtraction apparatus

Arithmetic apparatus for floating point numbers

Test circuit, selector, and semiconductor integrated circuit

Multiplication device using semiconductor memory