An integrated circuit wafer is formed as a monolithic focal plane array having signal processing circuitry formed upon a first surface thereof and infrared detector elements formed upon a second surface thereof. A process for forming the same is also disclosed. The wafer has an array of waffle-like hollows formed upon one surface. The floor of each hollow has a dense array of small diameter vias formed thereon. The vias extend through the wafer to the second surface thereof. Conductive conduits are formed through the hollows and vias to connect infrared detectors on the second side of the wafer to their associated signal processing circuitry formed upon the first side of the wafer.

Monolithic focal plane array

A method for constructing an infrared detector array directly upon a detector interface device is disclosed. The detector interface device mechanically and electrically connects the infrared detector array to signal processing equipment. In a first embodiment of the invention encapsulated single crystalline material is formed within a cavity formed in a substrate. The encapsulated single crystalline material formed within the substrate cavity is suitable for use as a seed crystal for graphotaxial crystal growth of a detector element support layer across the surface of the substrate. Detector elements can then be formed upon the detector element support layer. In a second embodiment of the invention a plurality of detector element support layers can be formed within an array of cavities formed upon the substrate. An individual infrared detector element can then be formed directly upon each of the detector element support layers to form a detector array upon the substrate. The use of a non-single crystalline substrate such as an alumina ceramic material provides sufficient structural integrity and thermal stability for the substrate to serve as a detector interface device to reliably connect the infrared detector elements to Z-plane modules.

Detector interface device

A recessed element photosensitive detector array with optical isolation having an increased sensitivity to incident photons and having reduced crosstalk due to low angle of incidence photons is disclosed. The array comprises a substrate, a plurality of parallel elongate cavities formed within the substrate, photosensitive detector elements formed within the cavities, and an optical insulating layer adjacent each of said cavities to optically isolate the cavities from each other. The elongate cavities provide an increased detector element surface area which increases the sensitivity of the recesses element photosensitive detector array to incident photons. The increased sensitivity of the array is due to an increase in the probability of capturing incident photons. The optical isolation provided by the optical insulating layer substantially reduces crosstalk among adjacent detector elements for low angle of incidence photons. The increased probability of capturing incident photons eliminates the need for an anti-reflective coating.

Recessed element photosensitive detector array with optical isolation

The invention relates to a polycrystalline or amorphous substrate (14) having a single crystal layer (24) formed on the substrate to produce an array of photosensitive detectors as well as a forming method. The single crystalline layer is grown by graphotaxie, that is to say lateral epitaxy, on the non-single crystalline substrate. A seed crystal (16) of material comprising the layer to be developed is embedded in the substrate. The graphotaxiale growth occurs from the seed crystal and progresses across the surface of the substrate. Several methods for obtaining a graphotaxiale growth are described.

Graphotaxially formed photosensitive detector array.

A detector element signal comparator system is used for noise reduction and image enhancement by comparing the output of any detector signal processor within a module to the output of any other detector signal processor within the same module. The detector element signal comparator system has a comparator (51-59) for each detector signal processor (41-49), a comparator bus (71) to connect the output of any detector processor to the comparators of all other detector signal processors, a switch (61-69) for each detector signal processor to selectively connect each detector signal processor to the comparator bus, and an output bus (73) for communicating the comparator signal from the detector element signal comparator to the next stage of signal processing.

Detector element signal comparator system

A method and apparatus are disclosed for offsetting the DC level of a modulating signal input to a dual balanced modulator. The circuit is adapted to offset a high frequency modulation signal by an amount sufficient to provide the optimum percent modulation of a carrier signal applied to the dual balanced modulator. The offset level to be applied is dependent upon the desired percent modulation and is further affected by the operating modulation and carrier frequencies as well as their respective input power levels.

RF amplitude modulator/mixer

A low power level RF signal (applied at Port 1) is processed by a network formed of capacitors (30, 32), inductor (28) and resistor (24) which adds a DC offset level (applied at Port 3) thereby effectively increasing the power level of the RF signal. External switching circuits connected to the offset signal will be more responsive to the signal due to the effective power elevation.

George A. Clarius

Papers

RF amplitude modulator/mixer

Dc offset network for rf signals