The present invention logs events which occur in the target software, and stores these in a buffer for periodic uploading to a host computer. Such events include the context switching of particular software tasks, and task status at such context switch times, along with events triggering such a context switch, or other events. The host computer reconstructs the real-time status of the target software from the limited event data uploaded to it. The status information is then displayed in a user-friendly manner. This provides the ability to perform a logic analyzer function on real-time software. A display having multiple rows, with one for each task or interrupt level, is provided. Along a time line, an indicator shows the status of each program, with icons indicating events and any change in status.

Logic analyzer for software

A method and apparatus, for determining test coverage estimation for an electrical circuit (10) formed in accordance with an original high level description (21), uses a central processing unit (CPU 18). The CPU (18) accesses the description (21) and parses the high level language description (21) to allow for the generation of new code. This new code is intermixed with code from the description (21) to form a new high level description (22) which not only can be used to simulate the electrical circuit but can collect test coverage information. A simulation of the description (22) is performed using test vector inputs to simulate operation of the circuit (10) and estimate it's test coverage for the test vectors. Various warning/error messages are derived to indicate where the test vectors are lacking in test coverage.

Method and apparatus for inserting computer code into a high level language (HLL) software model of an electrical circuit to monitor test coverage of the software model when exposed to test inputs

The present invention provides a tool with which a DBA can analyze a VLDB at all levels of data storage, both logical and physical, to analyze performance problems. The invention is particularly applicable to systems in which database files are striped over multiple disk drives. In the present invention, storage of information is monitored at three levels: database files, file system files, and individual disk drives Parameters indicating the activity and performance level of each of the levels of storage are taken at selected intervals and stored. An analysis tool is provided that allows a DBA to select a time window during which the database performance is be assessed. The analysis tool has a map of the logical and physical arrangement of the database being monitored and allows a DBA to move from level to level of both logical and physical structures involved in storing the data while displaying I/O activity in an easily understood manner.

Method for improving performance of large databases

The present invention relates to a method, apparatus and system for managing virtual memory, in which a co-processor ( 224 ) is adapted to use virtual memory with a host processor ( 202 ). A host memory ( 203 ) is coupled to the host processor ( 202 ) to implement the virtual memory. The co-processor ( 224 ) includes a virtual-physical memory mapping device ( 915 ) for interrogating a virtual memory table and for mapping one or more virtual memory addresses ( 880 ) requested by the co-processor ( 224 ) into corresponding physical addresses ( 873 ) in the host memory ( 203 ). The virtual memory table is stored in two or more non-contiguously addressable regions of the host memory ( 203 ), and is preferably a page table. The memory mapping device ( 915 ) further includes a multiple-entry translation lookaside buffer ( 889 ) for caching virtual-to-physical address mappings ( 872 ), where entries in the buffer ( 889 ) are replaced on a least recently used replacement basis. The memory mapping device ( 915 ) also includes devices ( 901 ) for comparing, replacing, singly invalidating and multiply invalidating one or more entries of the translation lookaside buffer ( 889 ). It also includes a hashing device ( 892 ) for, upon an occurrence of a miss in the translation lookaside buffer ( 889 ), hashing a virtual memory address ( 880 ) using a hash function to produce an index into the virtual memory table.

Method, apparatus and system for managing virtual memory with virtual-physical mapping

Method and apparatus for creating benchmark programs for the analysis of java virtual machine implementations are implemented. Java applications and applets are compiled into an intermediate code referred to as byte code. The Java byte code forms the machine code for the Java Virtual Machine. The Java Virtual Machine running on top of a hardware platform translates the byte code into native machine code for execution on the hardware platform on which the Java Virtual Machine is running. The performance of a Java Virtual Machine is improved by the use of a so-called "just in time" (JIT) compiler that translates commonly occurring sequences of bytes codes in the native instruction sequences which are then stored for later execution. Critical to the performance of the JIT is the ability of the JIT to optimally compile for the most commonly occurring sequences of byte codes. The method and apparatus for creating benchmark programs provides a means for performance measurements with respect to such sequences.

Method and apparatus for benchmarking byte code sequences

A method and apparatus as described for predicting the performance of a computer system. A benchmark program is run on an existing host computer, and is monitored to determine the actual sequence of instructions in the instruction set of the host. These are then converted into the corresponding sequence in the instruction set of the target. The performance of the target system in executing these instructions is then determined.

Method of predicting the performance of an emulated computer system

of EP0486154A virtual memory system comprises a main memory and a virtually addressed cache memory. The main memory holds address translation tables (segment tables, page tables) for translating a virtual address into a real (physical) address using predetermined fields of the virtual address to index the translation tables. Copies of recently used translation table entries are also held in the cache memory, to allow fast access to these entries without the need for a main store access. These copies are addressed by means of an address derived from the same predetermined fields as are used to index the translation tables.

Method of operating a virtual memory system

A data processor is provided with a mechanism for controlling its performance. The processor is allowed to run normally for R clock beats, and then further instruction starts are inhibited for W clock beats. The ratio W/R determines the level of performance of the processor.

Data processing apparatus and method with performance control

A benchmark program is run on an existing host computer, and is monitored to determine the actual sequence of instructions in the instruction set of the host. This sequence is then converted into the corresponding sequence in the instruction set of a target computer. The performance of the target system in executing these instructions is then estimated. There is also disclosed a method of performing a range definition test on a simulated target model.

George Allt

Papers

Method of predicting the performance of an emulated computer system

Method of operating a virtual memory system

Data processing apparatus and method with performance control

Predicting the performance of a computer system