An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Microelectronic packages and methods therefor

A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.

Stackable ball grid array package

Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.

Packaging methods and structures using a die attach film

A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.

Method for fabricating stackable chip scale semiconductor package

A microelectronic package (10) is formed by placing a lead frame (22) onto an adhesive polyimide tape (38). The lead frame (22) includes a plurality of metallic leads (16) and an opening. An integrated circuit die (12) is positioned onto the molding support (38) within the opening such that a non-active face (32) of the integrated circuit die (12) rests against the molding support (38). Wire leads (18) connect an active face (28) of the integrated circuit die (12) to the metallic leads (16). A plurality of metallic bumps (20) are attached to the metallic leads (16), and a polymeric precursor is dispensed. The precursor embeds the active face (28) of the integrated circuit die (12), the inner surface (19) of the metallic leads (16), the wire leads (18), and the metallic bumps (20). The microelectronic package (10) is then heated to cure the polymeric precursor to form a polymeric body (14). The microelectronic package (10) is then capable of being tested and subsequently attached to a printed circuit board (40) to form a low-profile microelectronic assembly (11).

Low-profile microelectronic package

In an electronic package, a solder connection (14) for bonding faying surfaces (31, 40) is formed of tin-bismuth alloy comprising a tertiary metal, preferably gold or silver, in an amount effective to increase the melting temperature of the alloy and enhance mechanical properties of the connection at elevated temperatures typically encountered during operation. A process for forming the solder connection comprises applying a film (36) of the tertiary metal onto at least one faying surface (31) and thereafter applying tin-bismuth solder paste (38) onto the film. Preferably, a plate (26) of tin-bismuth alloy is first electroplated onto the faying surface (31), onto which the tertiary metal is plated. During heating to reflow the solder, the tertiary metal dissolves to produce a uniform liquid that forms the connection.

Tin-bismuth solder connection having improved high temperature properties, and process for forming same

A method for producing a coating composed of an electroless metal plate, such as a copper plate, tightly bonded to a polyimide layer comprises a multi-step cure of the polyimide layer carried out in combination with a palladium-catalyzed electroless deposition process. A solution of a polyamic acid compound that is the precursor for the desired polyimide resin in a vaporizable solvent is applied to a substrate and heated preferably to temperature below 250° C., to form a soft-cured polyimide film. The film is immersed in an aqueous palladium-tin colloidal suspension to deposit the colloidal particles thereon, which particles are then activated to form palladium nuclei dspersed on the surface. The soft-cured film is then heated, preferably above about 250° C., to vaporize residual solvent and form a hard-cured polyimide layer having the palladium nuclei dispersed on the surface. The hard-cured layer is immersed in an electroless metal plating solution, whereupon the palladium nuclei catalyze deposition of the metal to form a continuous plate. In one aspect of the method, the metal-clad layer is further heated between about 350° C. and 450° C. to final cure the polyimide. It is found that the plate of the coating formed by this multi-cure method strongly adheres to the polymer layer to permit extended deposition and thereby form a relatively thicker plate without catastrophic separation from the polymer.

Polyimide coating having electroless metal plate

A variety of options exists for lithographically defining polyimides for microelectronics applications. The two investigated here, photosensitive polyimide and wet etching of low-stress polyimides, offer lower cost, higher throughput solutions compared with dry etch processes. Via sizes of less than 25 μm and film thicknesses of greater than 14 μm are difficult to process using these techniques: however, for applications such as interlayer dielectrics for high-density packaging or solder masks for flip chip die attachment, these limitations may not be insurmountable. Photosensitive polyimide can be patterned with fewer steps, but the overall quality of the film in terms of surface planarity and residual stress is not as good as wet etching of conventional polyimide.

George Demet

Papers

Low-profile microelectronic package

Tin-bismuth solder connection having improved high temperature properties, and process for forming same

Polyimide coating having electroless metal plate

Polyimides for electronics applications

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