A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Devices and methods with programmable logic and digital signal processing regions

An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

Dual processor digital audio decoder with shared memory data transfer and task partitioning for decompressing compressed audio data, and systems and methods using the same

A method for synchronizing stream processing with a locally generated system time clock is disclosed. A program clock reference is recovered from a transport layer and used to vary the frequency of the locally generated system time clock. A presentation time stamp is recovered from a packetized elementary stream derived from the transport layer. The relationship between a reference sample associated with the presentation time stamp from the packetized elementary stream and a current sample being streamed is determined relative to the system time clock. Data samples are added or subtracted from a stream of data samples being streamed in response to the step of determining to establish a relationship between the stream of samples and the presentation time stamp relative to the system time clock.

Methods and circuits for synchronizing streaming data and systems using the same

A multiply-accumulate (MAC) unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said first and second operands, a Wallace tree adder for reducing the partial products and for selectively arithmetically combining the reduced partial products with said third operand, a final adder for generating a final sum, and a saturation circuitry for selectively rounding or saturating said final sum is provided. A dual MAC unit is also provided.

Multiplier accumulator circuits

A method of managing multiple channels of audio data in an audio system having multiple speakers. A first channel signal is selectively passed through a software high-pass filter to selectively drive a first one of the speakers. A plurality of channel signals are selectively summed in software to generate a composite signal and the composite signal passed through a software low-pass filter to selectively drive a second one of the speakers.

Audio bass management methods and circuits and systems using the same

A two-pass Multiplier/Accumulator Circuit is provided which performs various arithmetic operations on operands contained within an X Register 10 (FIG. 1) and a Y Register 20 and places the result in an Accumulator Register 40. The arithmetic operations are carried out by passing the product of the operands successively through an array of adders in the Adder unit 34. Each adder adds an appropriate multiple of the contents of the X Register to the Accumulator 40 or to the output of the previous adder. The multiples are selected according to the contents of the Y Register. The X and Y Registers are fully buffered so that additional data transfers and functions may be performed while an arithmetic operation is in progress in a "pipeline" manner. The circuit is also capable of indicating the maximum or minimum value in a sequence of numbers in response to a single computer instruction to the circuit.

Two-pass multiplier/accumulator circuit

Apparatus is described for enabling a first processor to 
cause a second processor to effect a transfer of data between 
the processors in accordance with data transfer commands 
sent from the first processor to the second processor. The 
processors each have a program instruction memory for 
enabling the processors to operate independently and 
simultaneously when no data transfer is occurring between 
them. The apparatus comprises data transfer circuitry con­
nected between the processors for enabling the data to be 
transferred. A program instruction decoder is associated 
with the second processor for normally decoding and 
executing instructions stored in the program instruction 
memory of the second processor when no data transfer is 
occurring. Routing circuitry carries the data transfer com­
mands from the first processor to the program instruction 
decoder for decoding and executing to provide signals to the 
data transfer circuitry to effect a transfer of data.

Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between said processors

Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between the processors in accordance with data transfer commands sent from the first processor to the second processor is described. The processors each have a program instruction memory for enabling the processors to operate independently and simultaneously when no data transfer is occurring between them, and the apparatus includes data transfer circuitry connected between the processors for enabling the data to be transferred, a program instruction decoder associated with the second processor for normally decoding and executing instructions stored in the program instruction memory of the second processor when no data transfer is occurring, and routing circuitry for carrying the data transfer commands from the first processor to the program instruction decoder for decoding to provide signals to the data transfer circuitry to effect a transfer of data.

George P. Chamberlin

Papers

Two-pass multiplier/accumulator circuit

Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between said processors

Processor interface circuitry for effecting data transfers between processors