A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Intermediate-grain reconfigurable processing device

A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.

Devices and methods with programmable logic and digital signal processing regions

A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA). The IFU directs reconfiguration operations, instruction fetch and decode operations, memory access operations, and issues control signals to the DOU and the AOU to facilitate instruction execution. The DOU performs data computations, and the AOU performs address computations. Each T-machine is a data transfer device having a common interface and control unit, one or more interconnect I/O units, and a second local time-base unit. The GPIM is a scalable interconnect network that facilitates parallel communication between T-machines. The set of T-machines and the GPIM facilitate parallel communication between S-machines.

System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

Data processing device and method

In a multiprocessor data processing system, modules are cascaded by means of intermodule buses. Each module comprises a data processing unit, a first memory, a logic cell array programmable into four input/output interfaces, a second memory and a specialized processing unit such as a digital signal processor (DSP). A first interface, the first memory and the data processing unit are interconnected by a module bus. A fourth interface, the second memory and the specialized processing unit are interconnected by another module bus. A feedback bus connects the second and third interfaces in the last and first modules for constituting a ring. Such a system is particularly intended for image recognition, such as digitalized handwritten digits for postal distribution.

Multiprocessor system with cascaded modules combining processors through a programmable logic cell array

We first show how systems coupling symbolic methods with sub-symbolic ones -the so-called hybrid systems- can solve efficiently problems by using advantages from the two types of methods. Then we present a new flexible multi-grain parallelism architecture, called ArMenX, and we show how hybrid systems can be executed on this machine.

Hybrid Systems on a Multi-Grain Parallel Architecture

This paper presents neural and hybrid (symbolic and subsymbolic) applications downloaded on the distributed computer architecture ArMenX. This machine is articulated around a ring of FPGAs acting as routing resources as well as fine grain computing resources and thus giving great flexibility. More coarse grain computing resources-Transputer and DSP-tightly coupled via FPGAs give a large application spectrum to the machine, making it possible to implement heterogeneous algorithms efficiently involving both low level (computing intensive) and high level (control intensive) tasks. We first introduce the ArMenX project and the main architecture features. Then, after giving details on the computing of propagation and back-propagation of the multi-layer perceptron on ArMenX, we will focus on a handwritten digit (issued from a zip code data base) recognition application. An original and efficient method, involving three neural networks, is developed. The first two neural networks deal with the 'reading process', and the last neural network, which learned to write, helps to make decisions on the first two network outputs, when they are not confident. Before concluding, the paper presents the work of integration of ArMenX into a high level programming environment, designed to make it easier to take advantage of the architecture flexibility.

http://ieeexplore.ieee.org/iel3/3550/10641/00493815.pdf

An efficient handwritten digit recognition method on a flexible parallel architecture

Current high-speed communication networks exhibit gigabit bandwidths. Nevertheless, applications cannot take advantage of these advances due to host interface and machine and system architecture limitations. Today, the main concern is to reduce the protocol overheads imposed on data transfers, minimizing memory copies and implementing off-host communication functions. We propose a novel architecture for real-time distributed systems using a 155Mbit/sATM network. The system is based on an intelligent communication interface board for PCs, which integrates a Transputer, an FPGA and a VRAM to implement flexible high level communication services. These services are multiple copy updates of distributed real-time data on monitoring machines, transfers of audio and video streams coming from several cameras. The main advantages of our architecture over traditional systems include the reduction of the multimedia load imposed on the host processor, the provision of an efficient real-time data service for applications, and the support of existing standard protocols such as TCP/IP for traditional data. The board is being developed and will soon be experimented on a platform with live applications. The interest of this work is reinforced by the fact that integration of a processor and FPGA on a single chip will be available in the near future. 

Keywords: Asynchronous Transfer Mode (ATM), high speed networks, communication interface architecture, Field Programmable Gate Array (FPGA), Transputer, real-time, distributed applications, multimedia

PC/ATM interface accelerator using reconfigurable technology

The system includes modules which are interconnected in cascade by intermodule buses (BI12 to BI(I-1)I). Each module (2i) comprises a data processing unit (20i), a first memory (21i), a logic means (22i) which is configurable into four input/output interface means, a second memory (23i) and a specialised processing unit (24i). A first interface means (221i), the first memory (21i) and the data processing unit (20i) are interconnected by a module bus (25i) while a fourth interface means (224i), the second memory (23i) and the specialised processing unit (24i) are interconnected by another module bus (26i). A feedback bus (BR) links the second and third interface means in the final and first modules (22i, 221) to constitute a ring. Such a system is particularly intended for recognition of an image, such as digitised handwritten figures for postal distribution.

Gerald Ouvradou

Papers

Multiprocessor system with cascaded modules combining processors through a programmable logic cell array

Hybrid Systems on a Multi-Grain Parallel Architecture

An efficient handwritten digit recognition method on a flexible parallel architecture

PC/ATM interface accelerator using reconfigurable technology

multiprocessor data processing system.