Lithography is a field in which advances proceed at a swift pace. This book was written to address several needs, and the revisions for the second edition were made with those original objectives in mind. Many new topics have been included in this text commensurate with the progress that has taken place during the past few years, and several subjects are discussed in more detail. This book is intended to serve as an introduction to the science of microlithography for people who are unfamiliar with the subject. Topics directly related to the tools used to manufacture integrated circuits are addressed in depth, including such topics as overlay, the stages of exposure, tools, and light sources. This text also contains numerous references for students who want to investigate particular topics in more detail, and they provide the experienced lithographer with lists of references by topic as well. It is expected that the reader of this book will have a foundation in basic physics and chemistry. No topics will require knowledge of mathematics beyond elementary calculus.

Principles of Lithography

A reticle consisting of a multiplicity of small openings corresponding to separate and distinguishable points is put in the reticle plane. This reticle is imaged down through an opening O in aperture plate AP. A corresponding multiplicity of spots are created at the image plane of the optical system. These spots have spot centroids relative to the original separate and distinguishable points in the reticle. These points, however, are deviated from their diffraction limited positions by the average of gradφ(u)) over the corresponding ray bundle. The opening O in the aperture plate samples a discrete portion of the entrance pupil. With points spread out over an area of size 2*NAo*za, ray bundles with chief rays covering the entire entrance pupil will be projected down to image plane IP. The above outlined procedure is extended to analyzing the wavefront at a multiplicity of field points over the entire lens train. The process includes using an aperture plate AP consisting of a multiplicity of openings O. Each opening O is centered underneath a neighborhood of points that is accepted into the entrance pupil of the imaging objective. Points passing through all openings O will produce in the wafer plane a number of spot arrays corresponding to the number of openings O. The totality of all the arrays of spots whose centroids can be measured and reconstructed yield an aberrated wavefront φ(u;x) at a number of discrete field points x.

Apparatus, method of measurement, and method of data analysis for correction of optical system

A process of measuring the radiant intensity profile of an effective source of a projection image system that has an effective source, an object plane, an imaging objective, an exit pupil, and an image plane. The improved process consists of selecting at least one field point and a corresponding aperture plane aperture and projecting a plurality of images of the selected field point through the corresponding selected aperture plane aperture at a plurality of various intensities of the effective source. By analyzing the recorded images of the effective source at various intensities it is possible to determine a radiant intensity profile of the image source at the selected field point.

In-situ source metrology instrument and method of use

An apparatus and method for manufacturing and using a calibrated registration reference wafer in a semiconductor manufacturing facility. A reference reticle consisting of a 2-dimensional array of standard alignment attributes is exposed several times onto a photoresist coated semiconductor wafer using a photolithographic exposure tool. After the final steps of the lithographic development process the resist patterned wafer is physically etched using standard techniques to create a permanent record of the alignment attribute exposure pattern. The permanently recorded alignment attributes are measured for placement error using a conventional overlay metrology tool. The resulting overlay error data is used to generate a calibration file that contains the positions of the alignment attributes on the reference wafer. The reference wafer and calibration file can be used to determine the wafer stage registration performance for any photolithographic exposure tool.

Reference wafer and process for manufacturing same

Typical advanced lithographic processes require an overlay tolerance that is approximately 30% of the minimum feature size. To achieve this metrology must be limited to an error budget of 3–5% of the minimum feature size. A discussion of the general use of overlay data for assessment of stepper performance is followed by an overview of key overlay metrology equipment performance parameters (Tool Induced Shift-TIS) and the interaction with the process (Wafer Induced Shift-WIS). The interactions between the target, the process and the equipment will also be reviewed. Finally, use of this information in a case study of overlay target design for Tungsten Chemical Mechanical Planarization (W CMP) will be presented. Relevant process data will demonstrate how such targets can be used to effectively monitor both stepper (systematic error) and metrology tool (random error) performance.

Overlay metrology: the systematic, the random and the ugly

This paper presents a quick and accurate method for determining optical column misalignment and degree of telecentricity of a precision wafer stepper using computerized electrical techniques. The trend toward increasingly difficult device design rules has driven the present demand for ultimate stepper performance, which requires the optimization of column alignment and telecentricity, along with the routine monitoring of standard parameters including translation, rotation, magnification, trapezoid and distortion. Device designs using a full-lens field and requiring complex processing, involving large topographical steps, are especially demanding.

Electrical Methods For Precision Stepper Column Optimization

The typical pattern quality specifications for large lithography equipment (such as raster scan e-beam systems) and the industry standard pattern quality specifications for masks and reticles have grown to be quite different. The equipment manufacturers speak one language, the mask users speak another, and the mask maker must understand both. However, the relationship between these two sets of specifications is not obvious or typically available to the mask maker when purchasing such equipment, making it difficult to anticipate the mask and reticle quality it will deliver. The specific definitions and measurement procedures behind the Position Accuracy, Overlay Accuracy, Orthogonality, Scan Linearity and Linewidth Uniformity specifications for electron beam systems are examined in detail and their relationship to the Composite Overlay Errors and Composite Critical Dimension Variations found on masks and reticles is explored.

Mask Specs And Equipment Specs - Disparity And Reconciliation

A high resolution, easy to implement bilayer PMGI [poly[dimethylglutarimiden process has been developed for producing polysilicon gates for high density CMOS. One micron wide, proximity effect free, and very uniform poly lines were obtained. Unbiased mask dimensions were reproduced easily with optimum process latitude. A focus latitude of 5 microns for 1 micron dense (repeating line/space) pattern is reported. This was achieved using a conventional stepper with a nominal resolution of 1.1 microns and a depth of focus of +/-1.3 microns. The delta between the mask and the final wafer dimensions was virtually the same for lines ranging from 5 all the way to 1 micron, as well as for all single and dense lines showing no proximity effects. The after-etch linewidths were uniform to within a sigma of 0.04 microns across a 4 inch wafer. The process consisted of the following: The polysilicon was coated with a planarizing and antireflecting PMGI layer of about 1 micron. A 0.7 micron layer of conventional novolak resist was put on top. The image was formed in the top resist and transferred to the bottom by a deep UV flood exposure. The PMGI was developed in a aqueous-based solution completely removing the top resist in the process. The etching was done in a single wafer RIE machine. All the linewidth measurements were made on final poly structures using electrical techniques. The advantages of using PMGI over conventional materials such as PMMA are no interlayer mixing, aqueous-based developer chemicals, and better etch resistance. The process is very flexible and different schemes can be implemented as needed. A novolak cap can be retained for increased etch resistance by changing to a different aqueous developer solution; however, the simple uncapped approach was found to be already far superior to any single layer resist technique and it was easily implemented on conventional production equipment.

Optimization Of A Bilayer Resist Process For Polysilicon Gate Lithography

Process technologies developed for the fabrication of Application Specific Integrated Circuits must satisfy some unusual demands imposed by design automation and by fast turn around manufacturing.



In this paper we will discuss some of the problems that constrain the selection of a suitable interconnection technology for ASIC's VLSI.



Design automation (a tool necessary for ASIC designs) demands a simple set of design rules and very large current carrying capability metal Lines. On the other hand fast turnaround manufacturing requires the use of simple and proven technologies so that the product will be easily manufacturable, possibly in more than one foundry.



Some of the available technologies to implement mutilevel interconnections will be reviewed and the one chosen by VLSI Technology for their 1 μm ASIC process will be briefly described.

Gianpaolo Spadini

Papers

Electrical Methods For Precision Stepper Column Optimization

Mask Specs And Equipment Specs - Disparity And Reconciliation

Optimization Of A Bilayer Resist Process For Polysilicon Gate Lithography

Interconnections in application specific VLSI