A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Filler cells for design optimization in a place-and-route system

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.

Integrated circuit layout having mixed track standard cell

A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals, and defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal. The method further includes arranging selected cells from the cell library to form a desired layout of an integrated circuit, and routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells.

Method of making an integrated circuit using pre-defined interconnect wiring

Methods and circuits for optimizing performance and power consumption in a circuit design and circuit employing one or more lower threshold voltage (Lvt) cells or devices are described. A base supply voltage amplitude is determined for providing operating power for the circuit. The base supply voltage amplitude is a low or lowest voltage level that still satisfies a performance specification for the circuit. Providing a low or lowest base supply voltage level reduces or minimizes the standby (i.e., non-switching) power consumption in the Lvt device(s) since current leakage is reduced as the supply voltage level is reduced. Reducing the supply voltage level used to power the Lvt device(s) also reduces active power consumption for the circuit as well. Thus, total power consumption is optimized or reduced while still receiving the benefit of using Lvt devices to optimize or increase performance of a circuit layout and circuit.

Methods and circuits for optimizing performance and power consumption in a design and circuit employing lower threshold voltage (LVT) devices

In an integrated clock gating (ICG) cell a latch is coupled to a NOR gate. The NOR gate receives an enable signal. The latch is configured to generate a latch output in response to the state of the enable signal. The latch includes a tri-state inverter. A NAND gate is coupled to the latch and the NAND gate is configured to generate an inverted clock signal in response to the latch output and a clock input.

Low clock-power integrated clock gating cell

Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).

Generation of standard cell library components with increased signal routing resources

A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan enable, and is given to a transmission gate. A master latch is coupled to the transmission gate and to a tri-state inverter. The master latch is configured to receive an output of the transmission gate. A slave latch is configured to receive an output of the tri-state inverter and the multiplexer output. A data inverter is coupled to the slave latch. The data inverter is configured to generate a flip-flop output. A half clock gating inverter is configured to generate an inverted clock input in response to a clock input and the multiplexer output.

Low power clock gated flip-flops

A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate coupled to a tri-stated AND gate. A tri-state inverter is coupled to an output of the master latch and a slave latch is configured to receive an output of the tri-state inverter. A delay element is coupled to the slave latch, where the delay element is configured to delay a first output of the slave latch in response to the scan enable to generate a dedicated scan output.

High density low power scan flip-flop

An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

Girishankar Gurumurthy

Papers

Low clock-power integrated clock gating cell

Generation of standard cell library components with increased signal routing resources

Low power clock gated flip-flops

High density low power scan flip-flop

Performance and Area Scalable Cell Architecture Technology