A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

Gate circuit of combined field-effect and bipolar transistors

An off-chip driver (OCD) circuit is described including a first output device and a second output device having a common output connection wherein a rising (1 bit) or falling (0 bit) signal is applied through an input circuit 24 to the output devices. The output signal which appears at the common output connection will exhibit a rise time and a fall time corresponding to the rise and fall of the input signal. A first monitoring device is connected to the output signal to monitor the rise time of the output signal and a second monitoring device is connected to the output signal to monitor the fall time of the output signal. A ramp generator is provided which generates a reference signal which also includes a rise time and a fall time. The two monitor circuits and compare the rise and fall times of the output signal with the reference rise time and reference fall time to produce a feedback signal to control the rise and fall times of the output signal in accordance with the reference signal.

Driver circuit for controlling signal rise and fall in field effect transistor circuits

A pulse width modulator (PWM) system (100) detects several load current conditions to completely correct for the distortion caused by deadtime insertion when driving an inverter-fed inductive load, such as a three-phase AC motor. The system includes an inexpensive voltage sensor (140) which senses the output voltage at the end of each successive dead time interval in which neither a pullup transistor (51) nor a pulldown transistor (52) is driving. The system (100) includes a programmable PWM (125), two storage elements (131,132) such as D-type flip flops, and a memory-mapped register (133). The register stores the output of the flip-flops to indicate a near-zero load current condition. When it detects this condition, the system (100) changes the duty cycle of the PWM output signals to yield output voltages and currents which more closely approximate a sine wave. The system (100) is particularly useful as part of a low-cost microcontroller (120).

Pulse width modulator (PWM) system with low cost dead time distortion correction

An output circuit includes a totem-pole output circuit for driving a power MOSFET (FETI). A pull-up circuit and a pull-down circuit drive the output node low or high as required. The circuit prevents the pull-up (20) and pull-down (30) circuits from simultaneously conducting current. The pull-up circuit has a pull-up threshold voltage and the pull-down circuit has a pull-down threshold voltage such that the pull-up circuit is turned off before the pull-down circuit is activated when the output node is switched from a high state to a low state and further wherein the pull-down circuit is turned off before the pull-up circuit is activated when the output node switches from a low state to a high state.

Power mosfet driver with cross-conduction current reduction

A bipolar transistor-complementary field effect transistor composite circuit is provided which includes a pair of first and second bipolar transistors each having a collector of a first conductivity type, a base of a second conductivity type and an emitter of a first conductivity type. Collector-emitter current paths of the bipolar transistors are connected in series to each other between first and second potentials, with a connection node providing an output of the composite circuit. Field effect transistors are respectively coupled between the bases and collectors of the bipolar transistors for controlling the on-off states of the bipolar transistors in opposite relationship to one another in response to an input signal provided to the composite circuit. Also, discharge arrangements are provided for the bases of the first and second bipolar transistors to discharge parasitic capacitance in the bases of the first and second bipolar transistors when they are turned off.

Bipolar transistor-field effect transistor composite circuit

An improvement in output rise time and a reduction in the parasitic power supply strike current is achieved in bipolar transistor logic circuits using an AC coupled feedback circuit. During the low to high transition of the output, an internal voltage is AC coupled to an amplifier which in turn provides a low impedance path at the base of a lower output drive transistor which is coming out of conduction.

Circuit to improve rise time and/or reduce parasitic power supply spike current in bipolar transistor logic circuits

An improved fall time is achieved in bipolar transistor logic circuits which have three-state outputs. The circuits comprise a logic input terminal which is coupled to a push-pull output stage to drive a three-state output terminal. A three-state input receives three-state control signals for holding the output transistors in their non-conducting, high impedance state. Improved speed is achieved by adding a feedback circuit to remove stored base charge from the upper output driver transistor and to supply base current derived from the load to the lower output driver transistor during high to low transitions of the output voltage.

Base drive boost circuit for improved fall time in bipolar transistor logic circuits

A TTL to high level translator having improved high state current drive includes a push-pull output stage and a lateral PNP transistor for supplying current drive when the translator is in a high state The output stage consists of a pair of Darlington connected transistors comprising an upper amplifier and a lower transistor amplifier connected in series with the upper amplifier A current transient suppressor circuit circuit is coupled with the bases of the pair of Darlington connected transistors for inhibiting power supply current spikes as the upper and lower amplifiers are alternately turned on and off in response to the TTL logic signal switching between upper and lower level states

Low level logic to high level logic translator having improved high state drive

A feedback circuit is provided between the output and the input of a lower transistor amplifier of a push-pull amplifier driver output stage to inhibit power supply transients as the amplifier output stage transitions rapidly from a low to high output state. Additionally, if the push-pull output stage is incorporated within a three state gate or the like, which gate shares a common bus with other like three state gates, the feedback circuit inhibits loading of the bus whenever the three state gate is operated in a three state mode or is powered down as the other gates are active and are rapidly transitioned between low and high output states. The feedback circuit provides a low impedance path at the input of the lower transistor amplifier of the push-pull driver output stage to shunt transient currents harmlessly away from the base thereof to prevent the transient currents from turning on the lower transistor amplifier.

Miller capacitance effect eliminator for use with a push-pull amplifier output stage

Circuit de commutation en H (10) permettant de fournir une commande en courant a une charge couplee entre une premiere (20) et une deuxieme (22) sorties, comprenant un premier et un deuxieme circuits a transistors de commutation en couple, chacun comprenant un transistor superieur (12:16) qui est interconnecte au niveau de la premiere et de la deuxieme sorties a un transistor inferieur respectif en couple (14:18). H switch circuit (10) for providing a control current to a load coupled between a first (20) and a second (22) outputs, comprising a first and a second switching transistor circuitry couples, each comprising a upper transistor (12:16) which is interconnected at the first and second outputs to a respective lower transistor couples (2:18 p.m.). Les paires respectives de transistors de commutation sont rendues alternativement conductrices, ce qui permet de renverser la polarite de la commande en courant de la charge. The respective pairs of switching transistors are alternately rendered conductive, thereby spilling the load current polarity of the order. Un premier (56) et un deuxieme (58) transistors sont prevus, chacun etant couple respectivement entre un transistor inferieur de l'un des circuits a transistor de commutation en paire et les transistors superieurs de l'autre circuit a transistors de commutation en paire, de maniere a limiter considerablement les pointes de courant qui se manifestent autrement pendant la commutation au niveau des sorties du circuit de commutation. A first (56) and a second (58) transistors are provided, each being coupled respectively between a lower transistor of a pair of circuits in switching transistor and the upper transistors of the other pair circuit in switching transistors so as to significantly limit the current peaks that otherwise occur during the switching at the outputs of the switching circuit.

Gordon H. Allen

Papers

Circuit to improve rise time and/or reduce parasitic power supply spike current in bipolar transistor logic circuits

Base drive boost circuit for improved fall time in bipolar transistor logic circuits

Low level logic to high level logic translator having improved high state drive

Miller capacitance effect eliminator for use with a push-pull amplifier output stage

Switch circuit having improved switching characteristics