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Design Of Analog Cmos Integrated Circuits

A novel approach to filter design, based on Adams' [1] ‘log-domain’ filters, is proposed that yields a truly current-mode circuit realisation. Adams' idea, which was introduced in a limited context, is generalised to permit a complete distortionless synthesis procedure, which results in circuit implementations readily realisable using complementary bipolar processes. It is shown that, by introducing an exponential map on the state-space description of the desired linear system, a log-domain filter can be fully realised with transistors configured in current mirror-type groupings, current sources and capacitors. Owing to the mapping, the state variables are intrinsically related to current, and not voltage, in the resulting circuits, a fact that emphasises the current-mode nature of the design. A general biquadratic filter section is designed, and, following discussion of cascading sections, a seventh-order Chebychev lowpass filter is designed. All designed circuits are shown to be tunable over a two-decade range in frequency while their characteristics are accurately preserved, even for biquad sections whose f0Q product is greater than fT/10. The Chebychev filter is shown in simulation to possess nearly 60 dB dynamic range relative to 0.9% THD, with a cutoff frequency of nearly 5 MHz, using transistor models from AT&T's CBIC-R 300 MHz complementary bipolar process.

Log-domain filtering: an approach to current-mode filtering

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

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Computer-aided design of analog and mixed-signal integrated circuits

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

The author presents a discussion on several methods that can be used to improve the testability of mixed-signal integrated circuits. He begins by outlining the role of test, and its impact on product cost and qualify. A brief look is taken at the pending test crises for mixed-signal circuits. Subsequently, the author outlines several common test strategies, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. In the remainder of the paper he describes several analog test buses and circuits for built-in self-test applications.

http://ieeexplore.ieee.org/iel3/4814/13308/00606616.pdf

Improving the testability of mixed-signal integrated circuits

Foreword R. Adams. Preface. 1. Introduction. 2. Log-Domain Integrators. 3. Log-Domain Filter Synthesis-I: Operational Simulation of LC Ladders. 4. Log-Domain Filter Synthesis-II: State-Space Formulation. 5. Nonideality Analysis of Biquadratic Log-Domain Filters. 6. Extending the Nonideality Analysis to High-Order Ladder Filters. 7. Experimental IC Prototypes. Appendices. References. Index.

Design and Analysis of Integrator-Based Log-Domain Filter Circuits

Built-in-self-test (BIST) for VLSI systems is desirable for production-time testing and in the field diagnostics. This paper discusses a Mixed Analog Digital BIST (MADBIST) for a frequency response test and an intermodulation distortion test of an Analog-to-Digital converter. The MADBIST strategy for the FR and IMD tests of the ADC is introduced, accuracy issues are discussed, and preliminary experimental results are presented. >

A BIST technique for a frequency response and intermodulation distortion test of a sigma-delta ADC

In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single-stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.

Timing measurement device using a component-invariant vernier delay line

In this paper we present a new perspective on time amplification and its application to timing measurements on the Femto-second time scale. A simple yet practical circuit implementation for the amplification of the time between discrete (digital) events is introduced. Some metrics and figures of merit and performance are defined and parallels with the traditional amplification of "traditional physical" quantities, such as voltage and current, are drawn. The time amplifier (TAMP) has a dynamic range span from a few hundreds of Femto-seconds to a few hundreds of pico-seconds.

Gordon W. Roberts

Papers

Improving the testability of mixed-signal integrated circuits

Design and Analysis of Integrator-Based Log-Domain Filter Circuits

A BIST technique for a frequency response and intermodulation distortion test of a sigma-delta ADC

Timing measurement device using a component-invariant vernier delay line

A CMOS time amplifier for Femto-second resolution timing measurement