PURPOSE:To give guidelines regarding a fault tracing direction, by a method wherein the theoretical depth and the direction of signal propagation of a designed wiring pattern corresponding to a pattern appearing in an image of a difference between an article to be tested and a good article are given to the designed wiring pattern and displayed. CONSTITUTION:An observation image of a sample of an integrated circuit 3 to be tested, which is obtained from an electron beam test apparatus 1, and a normal operation state image for reference which is stored beforehand in a memory circuit 5 for an image for reference are subjected to a difference processing in a fault image forming circuit 6, and a fault image is formed and displayed in a fault image display element 7. A fault search map is prepared and displayed in the following procedure. First a fault pattern discriminating circuit 70 discriminates the length of the fault pattern, the coordinates of end points thereof, etc., on an observed fault image, as form parameters. Based on the fault pattern, the result of recognition by a design wiring recognizing element 80 is stored in a memory 2. A logical depth recognizing circuit 10 reads the logical depth of a circuit network and the terminal position of a logic cell and stores them in a memory 3. The data in the memories are displayed by a display element 12.

Testing apparatus for integrated circuit

PURPOSE:To positively acquire and apply suitable diagnostic knowledge in a simple manner by linking nodes representing a phenomenon within a process with an arc representing the correlation of the nodes on the basis of the structure of devices for the process thereby to obtain an oriented graph, and constructing a network model for each arc which sets an influential factor indicating the degree of influences between the nodes. CONSTITUTION:Such an abnormality is considered that an indication LI1 of a level meter 61A is not coincident with an actual level LA1. Therefore, nodes 71, 72 which represent the actual level LA1 and indication LI1 of the level meter, and the arc 71A are set. A node 73 of a PID attribution is set for an adjuster 64 corresponding to its function. Moreover, when the actual level LA1 becomes low and a pump 66 sucks in vain, the actual flow rate FA2 is turned to zero and therefore, a node 81 of a transient attribution (MORE attribution) is set. An influential factor is set for each arc. The influential factor is distinguished between positive and negative in accordance with the influential relation between the phenomena of nodes, and moreover indicated by a continuous value of -1.0-1.0. Accordingly, a network model 70 is formed.

Diagnostic method for process abnormality

PURPOSE:To achieve a higher speed of diagnosis of a large logical circuit, by finding a sequence circuit searching a loop matrix of directed graph to divide it into blocks of a combination circuit. CONSTITUTION:A flip flop is made up of gates G14 and G15 and a trouble diag nosing of a logical circuit containing a loop connection for making a feed back from the gate G14 to a gate G8 is conducted with an electron beam tester, a laser probe or the like. With gates G1-G15 considered as contacts, the logical circuit is divided into blocks of a combination circuit detecting the existance of a loop of a partial graph generated with inter-gate nets 1-29 made corre sponding to directed branches in such a manner that each line of the loop ma trix will surely contains 1 and -1 1 elements. The partial graph is formed by adding directed arms and contacts along the direction of the circuit from input terminals a-o. Furthermore, when additional arms are provided to form a large graph, the arm finally added shall be arranged to be a cut branch be tween the blocks if the element of each line in the matrixes is neither 1 nor -1 with the addition thereof.

Division for combination circuit of sequence circuit

PURPOSE:To reduce the time required for trouble shooting with a high-efficiency measurement of internal condition, by dividing an internal circuit of a logical LSI into blocks of respective combination circuit units to detect a defective element by discriminating operation. CONSTITUTION:A combination circuit block divider 10 discriminates a logical circuit data of an LSI 7 to be tested read out of an auxiliary memory 2 and when a sequence circuit is found, it divides the circuit into block of a combination circuit. Then, the divider applied a position data to stage controller 5 to move the LSI 7 to an intended position, where the LSI is irradiated with an electron beam from a tester 6 to analyze and the results are outputted to a comparator 9. The comparator 9 compares the results with a block-based expected value applied directly from the divider 10 to judge input/output state and when the state is not normal, the affected block is started to operate in a pattern leading to an abnormality while the output state of each element is checked in the direction opposite to the delay in the signal from an output terminal of each block sequentially with the tester 6 to detect an abnormal element in a short time.

Goto Yoshiaki

Papers

Division for combination circuit of sequence circuit

Internal diagnosing apparatus for integrated circuit