A DC/DC power conversion apparatus includes a reactor connected to a DC power supply and a DC voltage conversion section connected to the reactor. The DC voltage conversion section includes a plurality of switching devices, a charge-discharge capacitor which is charged or discharged by ON/OFF operations of the switching devices, a plurality of diodes which provide a charging route and a discharging route for the charge-discharge capacitor. The DC/DC power conversion apparatus also includes a smoothing capacitor on an output side, which is connected to the DC voltage conversion section and including a plurality of voltage division capacitors connected in series to each other, and a switching device for voltage equalization provided on a connection line provided between the negative terminal of the charge-discharge capacitor and a connection point between the voltage division capacitors.

Dc-dc power conversion apparatus

To reduce in-rush currents into a switched capacitor DC/DC converter and detect voltage and current faults, a converter controller is housed along with a current limit series transistor and fault detection circuitry. The series transistor is controlled to limit the in-rush current to a predetermined maximum level during start-up. If the duration of the current limit level, or the time for Vout to achieve a target voltage, exceeds a first threshold time, a first fault detector in the package shuts off the series transistor. During steady state operation, if the input current reaches the limit for a second threshold time or if Vout extends outside a certain range for the second threshold time, a second fault detector in the package shuts off the series transistor.

Switched capacitor DC-DC converter with reduced in-rush current and fault protection

A DC/DC power conversion device with smoothing capacitors including three column circuits share the smoothing capacitors to be connected in parallel, each column circuit have a plurality of circuits connected in series where two MOSFETs are connected in series between both ends of respective smoothing capacitors and LC serial bodies of capacitors and inductors with the same resonant cycle are disposed between the circuits at two middle terminals. Driving signals for the respective column circuits have the same driving cycle identical with the resonant cycle of the LC serial bodies, and are out of phase with each other by 2π/3(rad), and thus charge-discharge currents towards the smoothing capacitors are circulated among the column circuits and ripple currents flowing through the smoothing capacitors are reduced.

DC/DC power conversion device

A synthetic ripple regulator including frequency control based on a reference clock. The regulator includes an error network, a ripple detector, a combiner, a ripple generator, a comparator network and a phase comparator. The error network provides an error signal indicative of relative error of the output voltage. The ripple detector provides a ramp control signal based on the input and output voltages and a pulse control signal. The combiner adjusts the ramp control signal based on a frequency compensation signal to provide an adjusted ramp control signal. The ripple generator develops a ripple control signal based on the adjusted ramp control signal. The comparator network develops the pulse control signal to control switching based on the error signal and the ripple control signal. The phase comparator compares the pulse control signal with the reference clock and provides the frequency compensation signal.

Synthetic ripple regulator with frequency control

A pulse control clock generator for a voltage regulator including a comparator, a window circuit, a filter circuit, a ramp circuit, and a current circuit. The comparator compares a ramp voltage with a compensation voltage and provides a corresponding pulse control signal. The compensation voltage is indicative of output voltage error. The window circuit adds a window voltage to the compensation voltage to provide a hysteretic voltage. The filter circuit filters the hysteretic voltage to provide a filtered hysteretic voltage, such that a difference between the compensation voltage and the filtered hysteretic voltage is reduced in response to a load increase. The ramp circuit provides a repetitive ramp voltage which ramps between the filtered hysteretic voltage and the compensation voltage based on the pulse control signal. The current circuit increases a slope of the ramp voltage in response to the load increase.

Pwm clock generation system and method to improve transient response of a voltage regulator

A voltage converter including a buck converter and a capacitive voltage divider. The converter includes four capacitors, a switch circuit, an inductor and a controller. A first capacitor is coupled between a reference node and a first output node which develops a first output voltage. A second capacitor is coupled between an input node and either the reference node or the first output node. The switch circuit couples a third capacitor between the reference and first output nodes in a first state of a PWM signal, and couples the third capacitor between the first output and input nodes in a second PWM signal state. The inductor is coupled to the third capacitor and provides a second output node coupled to the fourth capacitor providing a second output voltage. The controller controls the duty cycle of the PWM signal to regulate the second output voltage to a predetermined level.

Greg J. Miller

Papers

Voltage converter with combined buck converter and capacitive voltage divider

Method of converting input voltage, and voltage converter and electronic device implementing the same