Over the past 15 years many organizations have researched the use of Static-Random Access Memory (SRAM)-based Field-Programmable Gate Arrays (FPGAs) in space. Although the components can provide a performance improvement over radiation-hardened processing components, random soft errors can occur from the naturally occurring space radiation environment. Many organizations have been developing methods for characterizing, emulating, and simulating radiation-induced events; mitigating and removing radiation-induced computational errors; and designing fault-tolerant reconfigurable spacecraft. Los Alamos National Laboratory has fielded one of the longest space-based FPGAs experiments, called the Cibola Flight Experiment (CFE), using Xilinx Virtex FPGAs. CFE has successfully deployed commercial SRAM FPGAs into a low-Earth orbit with Single-Event Upset (SEU) mitigation and was able to exploit effectively the reconfigurability and customization of FPGAs in a harsh radiation environment. Although older than current state-of-the-art FPGAs, these same concepts are used to deploy newer FPGA-based space systems since the launch of the CFE satellite and will continue to be useful for newer systems. In this article, we present how the system was designed to be fault tolerant, prelaunch predictions of expected on-orbit behaviors, and on-orbit results.

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The Cibola Flight Experiment

Configuration Scrubbing Architectures for High-Reliability FPGA Systems Aaron Gerald Stoddard Department of Electrical and Computer Engineering, BYU Master of Science Field Programmable Gate Arrays (FPGAs) are being used more frequently in space applications because of their reconfigurability and intensive processing capabilities. FPGAs in environments like space are susceptible to ionizing radiation which can cause Single Event Upsets (SEUs) in the FPGA’s configuration memory. These upsets may cause the programmed user design on the FPGA to deviate from its normal behavior. Space missions cannot afford to allow important data processing applications to become corrupted due to these radiation upsets. Configuration scrubbing is an upset mitigation technique that detects and corrects upsets in an FPGA’s configuration memory. Configuration scrubbing periodically monitors an FPGA’s configuration memory utilizing mechanisms such as Error Correction Codes (ECCs), Cyclic Redundancy Checks (CRCs), a protected golden file, and partial reconfiguration to detect and correct upset memory bits. This work presents improved Xilinx 7-Series configuration scrubbing architectures that achieve minimal hardware footprints, competitive performance metrics, and robust detection and correction capabilities. The two principal scrubbing architectures presented in this work are the readback and hybrid scrubbers which detect and correct Single Bit Upsets (SBUs) and Multi-Bit Upsets (MBUs). Harnessing the performance advantages granted by the 7-Series internal Readback CRC scan, a hybrid scrubber built in software for the Zynq XZC07020 FPGA has been measured to correct SBUs in 8.024 ms, even-numbered MBUs in 13.38 ms, and oddnumbered MBUs in 21.40 ms. It can also perform a full readback scrub of the entire device in under two seconds. These scrubbing architectures were validated in radiation beam tests, where one of the architectures corrected MBUs as large as sixteen bits in a single frame.

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Configuration Scrubbing Architectures for High-Reliability FPGA Systems

Virtex-4VQ dynamic and mitigated single event upset characterization summary

FPGAs are becoming increasingly attractive for use in space applications due to their reconfiguration and signal processing capabilities, as well as their increasing speed and capacity. Traditional SRAM-based FPGAs, however, are highly sensitive to the ionising radiation environment in space, making them prone to radiation-induced memory upsets. In this thesis, design techniques for mitigating such upsets are implemented, tested and evaluated, with the purpose of enabling a replacement of conventional radiation-hardened or antifuse FPGAs with Xilinx commercial SRAM-based FPGAs.
A test framework using an exchangeable payload is developed for this purpose and run on a Xilinx Virtex-5 FPGA. A payload application is selected and used to test and compare the gains and costs related to different levels of redundancy and different FPGA configuration memory scrubbing methods. In comparing soft error mitigation methods, test results for availability, resource usage, mean time to failure and faults in time are considered. Realistic satellite orbit and radiation scenarios are considered, and a complete example application is presented.
The product of this work is a set of recommendations regarding the use of commercial SRAM-based FPGAs in space applications.

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SEU Mitigation Techniques for Advanced Reprogrammable FPGA in Space

Mitigation selection and qualification recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 field programmable gate arrays

Orbital, space-based, and extra-terrestrial applications are susceptible to the effects of high energy charged particles. Single-event upsets (SEUs) can alter the logic state of any static memory element (latch, flip-flop, or RAM cell) including the components of an embedded hard processor. These upsets are unavoidable but correctable for the logic around the processor in FPGA configuration memory. This application note describes mitigation techniques and corresponding design flow when using a Xilinx FPGA with an embedded processor (specifically the PowerPC ® 405 found in the Virtex™-4 FX family) in high-radiation environments. This example contains a block RAM scrubber example for block RAM blocks attached to the processor local bus (PLB) used for code execution. Since this technique cannot triplicate the PowerPC 405 (PPC405), the surrounding logic is mitigated as much as practically possible. Therefore, the user must determine if the system mitigation is sufficient for the target environment. Note: It is essential for the reader to have a basic understanding of the Xilinx tool flow using the Xilinx Platform Studio (XPS), triple-module-redundancy (TMR) techniques, the Xilinx TMRTool, and ISE™ software. An in-depth understanding of [Ref 1] is also essential. In addition, an understanding of VHDL design and practice is recommended.

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Greg Miller

Papers

Single-Event Upset Mitigation Design Flow for Xilinx FPGA PowerPC Systems