The security of cryptographic implementations relies not only on the algorithm quality but also on the countermeasures to thwart attacks aiming at disclosing the secrecy. These attacks can take advantage of leakages of the secret appearing through the power consumption or the electromagnetic radiations also called “Side Channels”. This is for instance the case of the Differential Power Analysis (DPA) or the Correlation Power Analysis (CPA). Fault injections is another threatening attack type targeting specific nets in a view to change their value. The major principle to fight the side-channel attack consists in making the power consumption constant. The masking method allows the designer to get a power consumption which has a constant mean and a variance given by a random variable. Another manner is the Hiding method which consists in generating a constant power consumption by using a Dual-rail with Precharge phase Logic (DPL). This paper presents an overview of the various logic styles that have been promoted in the last six years, with an emphasis on their relative advantages and drawbacks.

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Overview of Dual rail with Precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors

Realization of logic functions using ternary reversible logic is known to requirelesser number of lines as compared to conventionalbinary reversible logic. This aspect of ternary reversible logic has motivated researchers to explore various synthesis approaches in the past. Existing synthesis methods require additional lines (called ancilla lines)for synthesis, which is expensive from the quantum implementation pointof view. There is no reported work for ternary reversible logic synthesisthat require the minimum possible number of gates and also lines. Thisclass of synthesis methods is called exact synthesis. In this paper two exact synthesis methods for ternary reversible logic have been proposed for the first time, one based on booleansatisfiability (SAT) and the other based on level-constrained heuristic search technique. A permutation representing a reversible ternary truth table is given as input, and a reversible circuit consisting ofgeneralized ternary Toffoli gates that implements the permutationis obtained as output. Experimental studies have been carried out on various randomly generatedternary reversible functions.

Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates

Reversible logic is a new emerging technology with many promising
applications in optical information processing, low power (Complementary Metal
Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc.
In industrial automation, comparators play an important role in segregating
faulty patterns from good ones. In previous works, these comparators have been
implemented with more number of reversible gates and computational complexity.
All these comparators use propagation technique to compare the data. This will
reduce the efficiency of the comparators. To overcome the problem, this paper
proposes an efficient comparator using (Thapliyal Ranganathan) TR gate
utilizing full subtraction and half subtraction algorithm which will improve
the computation efficiency. The comparator design using half subtraction algorithm
shows an improvement in terms of quantum cost. The comparator design using full
subtraction algorithm shows effectiveness in reducing number of reversible
gates required and garbage output.

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Design and Implementation of an Efficient Reversible Comparator Using TR Gate

Reversible circuits have been intensively studied in recent years due to their applications in many areas, including quantum computing, nanotechnology and low-power design. Synthesis of reversible circuits differs significantly from the traditional logic synthesis. No satisfactory synthesis algorithm has been proposed for such circuits so far. All existing heuristic approaches to reversible logic synthesis utilize complexity measures. In this paper such complexity measures are analyzed and quantitative comparison of these approaches is presented. Possibilities for improving heuristic algorithms for reversible circuit synthesis are also discussed.

Estimating the quality of complexity measures in heuristics for reversible logic synthesis

Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. This paper proposes an analogic selection sorting algorithm essentially based on the transformation-based algorithm. It uses an unweighted, undirected graph for the representation of all transformable paths. During the synthesis process, a sequence of transformations are performed to enable all the output patterns to appear in the right place. The whole process can be implemented by a sequence of Toffoli gates. In addition, a simplification algorithm is put forward to further optimize the generated circuit. The experimental results show that this algorithm, compared with other exact methods, can achieve optimal or nearly optimal solutions with less computation time. Furthermore, it is more easily understood and implemented.

A Novel Transformation-Based Algorithm for Reversible Logic Synthesis

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Grosse

Papers

Fast exact toffoli network synthesis of reversible logic