Memristor based crossbar memories are prime candidates to succeed the Flash as the mainstream nonvolatile memory due to their density, scalability, write endurance and capability of storing multibit per cell. In this paper, we present a memristor crossbar memory architecture that utilizes a reduced constraint read-monitored-write scheme. The proposed scheme supports multibit storage per cell and utilizes reduced hardware, aiming to decrease the feedback complexity and latency while still operating with CMOS compatible voltages. We additionally present a read technique that can successfully distinguish resistive states under the existence of resistance drift due to read/write disturbances in the array. We also provide derivations of analytical relations to set forth a design methodology in selecting peripheral device parameters.

A Drift-Tolerant Read/Write Scheme for Multilevel Memristor Memory

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Bio-inspired Hardware Architectures for Memory, Image Processing, and Control Applications

This paper introduces an improved SPICE model of memristor using dependent sources and switches. The proposed SPICE model with two parameters in dependent current source has ideal frequency and amplitude characteristics. We simulate two circuits with memristor. The results demonstrate that the memristor can “remember” last resistance value when no current passes through it, the Amplitude Modulation (AM) circuit with memristor and op-amp is simulated under the condition of high frequency. Since the memristor has great performance in frequency there might be a possible application of the memristor to be used as modulator or demodulator in wireless communication.

Guang Yi Wang

Papers

An Improved SPICE Macromodel of Memristor for General Applications