A method and apparatus for coupling a plurality of channels of a communications network to a node. The node includes a plurality of ports, each adapted for connection to a corresponding channel and a system interface adapted for connection to a plurality of node clients in the form of host computers, peripheral devices, network interfaces, etc. The node includes a receiver and transmitter dedicated to each port and common circuitry for controlling and processing frames received and/or transmitted by the plurality of ports. A frame prioritization circuit forwards frames received by a selected port to a frame handler for processing and a frame routing circuit routes frames processed by the frame handler to at least one of the ports associated with at least one destination node. The node further includes a frame header buffer associated with each port for temporarily storing the header of each frame received by the respective port prior to forwarding of the header to the frame handler.

Method and apparatus for reordering frames

A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.

Hardware interface to a high-speed multiplexed link

A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to a parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations. Further flexibility is provided which permits the switching adapter to be personalized to support any one of a number of standard and proprietary serial protocols. A personalization PROM specifies the particular serial protocol that each individual adapter is to support. The parallel switching network becomes a flexible media that interconnects and allows different serial protocols to communicate with each other; i.e., any number of different serial protocols can interface with the same parallel switch network. This allows every node of the parallel system to send and receive messages using its own native protocol. However, a node is not restricted to communicating only with others nodes using the same protocol, but is can communicate with any of the other nodes regardless of the serial protocol they use.

Protocol-to-protocol translator for interfacing disparate serial network nodes to a common parallel switching network

A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes is the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to the parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations. A a parallel electrical switch can efficiently handle either optical or electrical serial data and utilize information via wireless gateways to provide the features required for parallel processing and "farm" approaches, such as low latency, high bandwidth, scalability, fault tolerance, and high reliability. In addition, further flexibility is provided which permits the switching adapter to be personalized to support the any one of a number of standard and proprietary serial protocols. A personalization PROM specifies the particular serial protocol that each individual adapter is to support. The parallel switching network becomes a flexible media that interconnects and allows different serial protocols to communicate with each other; i.e., any number of different serial protocols can interface with the same parallel switch network. This allows every node of the parallel system to send and receive messages using its own native protocol. However, a node is not restricted to communicating only with others nodes using the same protocol, but it can communicate with any of the other nodes regardless of the serial protocol they use. The switch enables generic networks with heterogeneous and/or homologous nodes as a computer system. It can replace LANs and WANs and provide high speed cluster switching. Applications include parallel processing with existing computers, and features of multiple processor computer system which transfer multi-media information from one or many senders to one or many receivers, useful in teaching and many other applications. The nodes of an asynchronous computer system are connected asynchronously in a non-blocking by search manner with connections for set up at 2 cycles per cascaded node and message transfer continues at maximum media transfer speed.

Multi-media serial line switching adapter for parallel networks and heterogeneous and homologous computer system

A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.

Integrated data link controller with synchronous link interface and asynchronous host processor interface

The Asynchronous Packet Manager is the interface for transferring data in a first format between a data terminal equipment and a combination data and telephone switching system in a properietary packet format. A microprocessor accepts data from a universal asynchronous receiver transmitter and forwards the data to a mini packet receiver transmitter, when it is formatted into mini packets and converted to an alternate mark inversion signal and sent to the switching network.

Asynchronous packet manage

The Synchronous Packet Manager is the interface for switching synchronous data between a data terminal equipment and a combination data and telephone switching system in a proprietary packet format. A first microprocessor controlled circuit controls data to be received from the switching system or forwarded to it and communicates with a second microprocessor controlled circuit for controlling data to or from a terminal equipment via a common memory.

Gulay Sencer

Papers

Asynchronous packet manage

Synchronous packet manager