Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.

High voltage tolerant supply clamp

A rubber composition and preparation method and vulcanized rubber thereof, the rubber composition comprising non-cross-linked rubber and cross-linked rubber particles dispersed in the rubber composition; the cross-linked rubber particles can be synthetic rubber particles and/or natural rubber particles, e.g. any one or more of the following: natural rubber particles, styrene butadiene rubber particles, carboxylated styrene butadiene rubber particles, nitrile rubber particles, carboxylated nitrile rubber particles, chloroprene rubber particles, polybutadiene rubber particles, silicone rubber particles or acrylate rubber particles, butadiene-styrene-vinyl pyridine rubber particles and the like, with an average particle diameter of 20-500nm, and gel content of 60% by weight or above; the non-cross-linked rubber is styrene butadiene rubber; and the weight ratio between the cross-linked rubber particles and the non-cross-linked rubber is 1:99-20:80. The rubber composition is obtained by mixing and solidifying the latex of the non-cross-linked rubber and the latex of the cross-linked rubber particles, the latex of the cross-linked rubber particles being the rubber latex processed by irradiation cross-linking. The rubber composition simultaneously improves the vulcanized rubber rolling resistance, wet-skid resistance and wear resistance, and can be used to prepare high performance tread rubber for automobiles.

Rubber composition and preparation method and vulcanized rubber thereof

Provided is a receiver circuit which receives an input signal. A first restriction circuit provides a first reference voltage or an input signal higher than the first reference voltage to a first node. A second restriction circuit provides a second reference voltage or the input signal lower than the second reference voltage to a second node. A first PMOS transistor pulls up an output node based on a voltage of the first node, and a first NMOS transistor pulls down the output node based on a voltage of the second node. A second PMOS transistor is connected between the output node and the first PMOS transistor, and a second NMOS transistor is connected between the output node and the first NMOS transistor. At least one compensation resistor is connected between a power supply voltage and the first PMOS transistor or between the first NMOS transistor and a ground.

Receiver circuit and signal receiving method thereof

The invention discloses a low-submarine-communication CMOS three-state output circuit, comprising an output drive tube gate end control circuit, a transmission gate logic circuit for preventing a gate end from causing electric leakage to a power supply end through a front buffer, a well potential bias circuit, a well bias tube gate voltage control circuit and an output drive circuit. The low-submarine-communication CMOS three-state output circuit disclosed by the invention has the following applications: 1, the circuit has a three-state output function after being powered; 2, an output port of the circuit has a cold backup function, which means that when the power supply voltage of the circuit is zero, the port has a high impedance state to the power supply or the ground; 3, during the decreasing of the power supply voltage, the output end of the circuit has the high impedance state to the power supply or the ground, which means that the isolation between the output end and a bus can be ensured, if a bus signal is a high level, an electric leakage path of the output port to the power supply or a ground terminal does not exist, and the circuit can be switched from a normal power-on state to a cold backup operation state; and 4, in the cold backup state, if the bus signal accessed to the output port is a high-low level variable signal, an electric leakage path of the port to the power supply or the ground does not exist, and the isolation between the output port and the bus can be ensured.

Low-submarine-communication CMOS three-state output circuit

The invention relates to an input/output receiving circuit comprising a receiving terminal, a first NMOS tube, a shaping circuit, and a compensation unit The receiving terminal is coupled with an external voltage A source electrode of the first NMOS tube is coupled with the receiving terminal and a gate is coupled with a first power supply voltage An input terminal of the shaping circuit is coupled to the first power supply voltage and a drain of the first NMOS tube and the shaping circuit is used for realizing shaping of a drain signal of the first NMOS tube The input terminal of the compensation unit is coupled with the first power supply voltage, the ground and the receiving terminal and the output terminal is coupled with a drain of the first NMOS tube; and the compensation unit is used for compensating the drain signal of the first NMOS tube, so that the maximum value of the drain signal voltage of the first NMOS tube can reach the first power supply voltage The performance of the input/output receiving circuit can be improved

Input/output receiving circuit

The invention provides a high-voltage tolerance output buffer, comprising an input module, a pulling up module, a pulling down module, an enable control module and a voltage limiting module, the input end of the input module is connected with an input signal and an output enable signal, the voltage limiting module is connected with an inverter, the output signal of the inverter controls the conduction of the voltage limiting module, and the input signal of the inverter is the non output enable signal; the high-voltage tolerance output buffer effectively improves the performance of a standard input and outlet circuit which is used as an open-drain circuit to output waveform, reduces the tolerant maximum voltage of a voltage limiting transistor, improves the reliability of the circuit and ensures the stable operation of the while circuit.

High-voltage tolerance output buffer

An ESD protection circuit and method for its use are provided. The circuit comprising: a discharge path formed by first and second NMOS transistors which are sequentially connected between a ground and a power supply; an ESD event detection unit; first and second drive units respectively connected between an output of the ESD event detection unit and a gate of the first transistor and between the output of the ESD event detection unit and a gate of the second transistor. The first and second drive units respectively cause the first and second transistors to be turned on during an ESD event and to be turned off when there is no ESD event.

Electrostatic discharge protection circuit and electrostatic discharge protection method

Electronic static discharge protection circuit and electronic static discharge protection method

A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage.

High-voltage-tolerant pull-up resistor circuit

The present invention provides an MOS transistor circuit having gate bias compensation. The MOS transistor circuit is characterized by at least including: a resistor element and an MOS semiconductor assembly which includes a first MOS semiconductor element and a second MOS semiconductor element; wherein the resistor element is connected to the first MOS semiconductor element in series, and the second MOS semiconductor element is connected to the resistor element and the first MOS semiconductor element via a gate. The MOS transistor circuit achieves gate bias compensation under different PVT process corners according to a characteristic that the resistance of a polycrystalline silicon is little influenced but the resistance of a MOS transistor is heavily influenced under different PVT process corners. Therefore, output current is basically not influenced by a PVT change and a decrease in the qualified rate of the circuits is prevented.

Guo Zhiguang

Papers

High-voltage tolerance output buffer

Electrostatic discharge protection circuit and electrostatic discharge protection method

Electronic static discharge protection circuit and electronic static discharge protection method

High-voltage-tolerant pull-up resistor circuit

MOS transistor circuit having gate bias compensation