In this paper, a silicon-based T-shape gate dual-source tunnel field-effect transistor (TGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the structure, characteristic, and analog/RF performance of TGTFET, LTFET, and UTFET are discussed. The gate overlap introduced by T-shape gate can enhance the efficiency of tunneling junction. The dual-source regions in TGTFET can increase the on-state current (ION) by offering a doubled tunneling junction area. In order to further improve the device performance, the n+ pocket is introduced in TGTFET to further increase the band-to-band tunneling rate. Simulation results reveal that the TGTFET’s ION and switching ratio (ION/IOFF) reach 81 μA/μm and 6.7 × 1010 at 1 V gate to source voltage (Vg). The average subthreshold swing of TGTFET (SSavg, from 0 to 0.5 V Vg) reaches 51.5 mV/dec, and the minimum subthreshold swing of TGTFET (SSmin, at 0.1 V Vg) reaches 24.4 mV/dec. Moreover, it is found that TGTFET have strong robustness on drain-induced barrier lowering (DIBL) effect. The effects of doping concentration, geometric dimension, and applied voltage on device performance are investigated in order to create the TGTFET design guideline. Furthermore, the transconductance (gm), output conductance (gds), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), and gain bandwidth (GBW) of TGTFET reach 232 μS/μm, 214 μS/μm, 0.7 fF/μm, 3.7 fF/μm, 11.9 GHz, and 2.3 GHz at 0.5 V drain to source voltage (Vd), respectively. Benefiting from the structural advantage, TGTFET obtains better DC/AC characteristics compared to UTFET and LTFET. In conclusion, the considerable good performance makes TGTFET turn into a very attractive choice for the next generation of low-power and analog/RF applications.

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Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor

In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges (ITCs) on dopingless (DL) NW-based device have been addressed for the first time. CP technique is used to induce charge carriers within the drain/source regions by depositing layers of metals with specific work function. Linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points are calculated including the effects of ITCs on the cylindrical channel–surround gate–oxide interface. This work shows that positive ITCs can help in improving the device characteristics, whereas negative ITCs degrade the device performance. The ON-state current to OFF-state current ratio decreases for either polarity of ITCs. The ON-state current has been improved by approximately 50% with higher positive ITCs. The presence of positive ITCs in DL NWTFET improves the driving capability to be used for analog applications. The linearity parameters tend to improve with positive ITCs and degrade with negative ITCs. The proposed device has reached the same cutoff frequency at lower operating gate bias (approximately 0.8 V) with half the threshold voltage for higher positive ITCs.

Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges

In this paper for the first time, the noise immunity and analog performance of nanotube junctionless field effect transistor (NJLFET) has been investigated. Small signal AC performance metrics namely Scattering parameters (S-parameters) have been analyzed along with analog parameters to validate the suitability of NJLFET for RFIC design. NJLFET performance is examined by comparing its performance with junctionless gate-all-around (JLGAA) MOSFET. It has been inferred that NJLFET has improved I
 on/I
 off ratio directing improved digital performance at higher channel lengths, reduced channel resistance (R
 ch) which enables the MOSFET to provide a low resistance path to current and improved early voltage (V
 EA) which shows the capability for high-gain amplification and higher g
 m/g
 d directing high intrinsic dc gain. Higher f
 Tmax for NJLFET has been observed posing its potential for terahertz applications. Higher gain transconductance frequency product makes NJLFET an ultimate device for high-speed switching applications. Higher maximum transducer power gain in NJLFET implies higher power gain than JLGAA MOSFET. Also, NJLFET exhibits lower harmonic distortion and it has been explained by significant reduction in third-order derivative of transconductance, g
 m3. Reduction in g
 m3 shows that NJLFET provides better linearity over JLGAA and is more suitable for RFIC design. Also the S-parameters namely S11, S12, S21 and S22 have been analyzed to verify the small signal performance. A lower magnitude for reflection coefficients S11 and S22 depicts minimum reflection and higher matching between ports in NJLFET than JLGAA MOSFET. Higher voltage gains S12 and S21 are present in NJLFET than its counterpart which shows the higher gains that can be achieved using nanotube architecture. The noise metrics which are noise figure and noise conductance show significant reduction for NJLFET justifying its noise immunity.

Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET)

To overcome the problem of fabrication complexity and to reducei the cost of microelectronic devices, a new concept of dual-material control gate with dual-oxide tunnel field-effect transistor is investigated. A stack gate approach is applied to reduce the width of tunneling barrier at source–channel junction. Use of dual oxides at source–channel interface provides improved capacitive coupling, which enhances the on-state current. The entire gate segment has been partitioned into three parts, namely tunnel gate $$(M_1)$$, control gate $$(M_2)$$ and auxiliary gate $$(M_3)$$ with different work functions such as $$\phi _{1}$$, $$\phi _{2}$$ and $$\phi _{3}$$. In this context, to keep dual-work functionality, the feasible combinations of these work functions are adopted. Technology computer- aided design (TCAD) simulations of these proposed combinations of work functions along with dual oxides provide better results for the combinations of $$(\phi _1=\phi _3<\phi _2)$$. In addition, comparison between these combinations on the basis of analog/RF performance is done in this work. This work shows improved analog/RF parameters such as $$g_\text {m}, C_\text {gs}, C_\text {gd}, f_\text {T}$$ and TFP, and linearity parameters including $$g_\text {m3}, \text {VIP3, IIP3}$$ and $$\text {IMD3}$$ for the proposed device DMDODG-TFET (dual-material dual-oxide double-gate TFET). The use of this proposed device structure reduces the ambipolar behavior and subthreshold swing $$(18.5\,\text {mV}/\text {deacde})$$, and enhances the on-current [$$3.6\times 10^{-5}\,(A/\upmu \text {m})$$] significantly, making it suitable for analog/RF and linearity applications.

Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance

Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation

1 Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi, India rakhinarang@gmail.com, mridula@south.du.ac.in 2 Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi, India saxena_manoj77@yahoo.co.in 3 Department of Electronics and Communication Engineering, Maharaja Agrasen Institute Of Technology, Sector-22, Rohini, Delhi, India rsgu@bol.net.in

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Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack

The paper presents a simulation study of effect of interface fixed charges on the performance of the cylindrical nanowire MOSFET for different channel materials (Si, GaAs and Ge). The objective of the present work is to study the effect of hot carrier damage/stress induced damage/process damage/radiation damage induced fixed charges at the semiconductor-oxide interface of the cylindrical nanowire MOSFET. Also the circuit reliability issues of the device are discussed in terms of the performance degradation due to interface fixed charges. The performance has been compared for the three materials in terms of drain current driving capability, Ion/Ioff ratio, early voltage, transconductance, parasitic gate capacitance, intrinsic delay, current gain and power gain of the device.

/pdf/impact-of-interface-fixed-charges-on-the-performance-of-the-1746rrl18i.pdf

Gupta

Papers

Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack

Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET