A Class D amplifier comprises a pulse width modulator and an output stage. In this paper we analyze the power dissipation mechanisms and derive the overall power efficiency of the output stage realized using the finger and waffle layouts. We compare the relative merits of these layouts; we propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): (1) optimization to a single modulation index point and (2) optimization to a range of modulation indexes. For the design of an output stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.

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Analysis and design of power efficient class D amplifier output stages

A digital hearing aid is provided that includes front and rear microphones, a sound processor, and a speaker. Embodiments of the digital hearing aid include an occlusion subsystem, and a directional processor and headroom expander. The front microphone receives a front microphone acoustical signal and generates a front microphone analog signal. The rear microphone receives a rear microphone acoustical signal and generates a rear microphone analog signal. The front and rear microphone analog signals are converted into the digital domain, and at least the front microphone signal is coupled to the sound processor. The sound processor selectively modifies the signal characteristics and generates a processed signal. The processed signal is coupled to the speaker which converts the signal to an acoustical hearing aid output signal that is directed into the ear canal of the digital hearing aid user. The occlusion sub-system compensates for the amplification of the digital hearing aid user's own voice within the ear canal. The directional processor and headroom expander optimizes the gain applied to the acoustical signals received by the digital hearing aid and combine the amplified signals into a directionally-sensitive response.

Digital hearing aid system

A digital to analog (D/A) converter (306) for hearing aids and the like includes a delta-sigma modulator (204) and a duty cycle demodulator (208). The delta-sigma modulator converts medium rate, high resolution data (202) into medium rate, medium resolution data (206), and the duty cycle demodulator converts the medium rate, medium resolution data into low resolution, high rate data (210). The duty cycle demodulator utilizes a lookup function (220) to format the output data in a format having lowered transition rates, resulting in lower power use. The delta-sigma converter may include a correction factor (93) in at least one of its feedback loops to compensate for the characteristics of the output data from the duty cycle demodulator.

Delta-sigma pwm dac for reduced switching

An invention providing a hard limiter (110) between the pulse width modulator (112) and output drive transistors (114) of a class-D amplifier is disclosed. The limiter (110) functions by controlling the duty cycle of the pulse width modulator output, which directly corresponds to the magnitude of the voltage appearing across the load output transducer. The pulse width modulated (PWM) signal is compared to the outputs of a pair of one-shot circuits (210) (single pulse generators). If either the positive pulse or the negative pulse of the PWM signal is shorter than the one-shot pulse, then the one-shot pulse is substituted for the PWM pulse. This sets the maximum and the minimum values for the duty cycle of the PWM signal, thereby limiting the positive and negative value of the corresponding output voltage.

Output limiter for class-D BICMOS hearing aid output amplifier

We investigate the influence of two important practical design parameters on total harmonic distortion (THD) for the design of low-voltage (0.9-1.4 V) low-power analog Class-D amplifiers: the linearity of the carrier waveform and the impedance of the output stage. We show that the carrier nonlinearity results in THD and propose a novel mathematical analysis method to model the nonlinearity. We recommend a range of the parameter that describes the carrier nonlinearity and that results in a good compromise to the dynamic range of the pulsewidth modulator of the Class-D amplifier. We show that the impedance of the output stage has little effect on THD. We verify our analyses by means of MATLAB and HSPICE computer simulations, and on the basis of practical measurements.

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An investigation into the parameters affecting total harmonic distortion in low-voltage low-power Class-D amplifiers

An invention, which is fabricated using a Bipolar and Complementary Metal Oxide Semiconductor (BICMOS) technology which offers both bipolar and CMOS devices on the same silicon substrate is disclosed. The major part of the internal circuitry uses bipolar devices while the output circuit driving the transducer at the output uses CMOS inverters. A voltage regulator which is fed from the battery lines is used to power the majority of the internal circuitry leaving only the CMOS output driver and part of a level converter to be powered directly from the battery lines. This architecture guarantees that no signal is fed back to the previous stages of the hearing aid system through the battery lines, ensuring stable operation for an extended range of the battery internal impedance value. The bipolar front-end blocks of the circuit are designed using low-voltage bipolar design techniques to operate at the 1 volt level produced by the internal voltage regulator. The voltage regulator employs a bipolar base-emitter voltage reference, which ensures the tracking of its output voltage with the headroom requirements of the bipolar circuitry over the temperature and process variations.

Gurcan Hakan Ates

Papers

Class-D BICMOS hearing aid output amplifier