Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log/sub 2/N stages with N/2 two-point butterfly modules for each stage. The method assumes that failures are confined to a single complex multiplier or adder or to one input or output set of lines. Such a fault model covers a broad class of faults. It is shown that only a small overhead ratio, O(2/log/sub 2/N) of hardware, is required for the networks to obtain fault-secure results in the first scheme. A novel data retry technique is used to locate the faulty modules. Large roundoff errors can be detected and treated in the same manner as functional errors. The retry technique can also distinguish between the roundoff errors and functional errors that are caused by some physical failures. In the second scheme, a time-redundancy method is used to achieve both error detection and location. It is sown that only negligible hardware overhead is required. However, the throughput is reduced to half that of the original system, without both error detection and location, because of the nature of time-redundancy methods. >

Fault-tolerant FFT networks

This paper considers the implementation of a fast Fourier transform (FFT) structure using arrays of read-only memories. The arithmetic operations are based entirely on the residue number system. The most important aspect of the structure relates to the scaling arrays, which are required to prevent overflow. Because of the limitations of the number system, scaling factors have to be chosen on an a priori basis. This paper develops optimum procedures for choosing both scaling factors and the position of scaling arrays in the structure. Some examples are presented relating to the filtering of speech via a convolutional filter structure.

Implementation of FFT structures using the residue number system

Heart Rate (HR) is one of the most important Physiological parameter and a vital indicator of peoples physiological state and is therefore important to monitor. Monitoring of HR often involves hig ...

https://www.ep.liu.se/ecp/129/002/ecp16129002.pdf

Real Time Heart Rate Monitoring from Facial RGB Color Video using Webcam

Implementation of FFT Structures Using the Residue Number System

The Fast Fourier Transform is a fundamental tool in scientific and technical computation. The highly parallelizable nature of the algorithm makes it a suitable candidate for GPU acceleration. This paper focuses on exploiting the speedup due to using the half precision multiplication capability of the latest GPUs' tensor core hardware without significantly degrading the precision of the Fourier Transform result. We develop an algorithm that dynamically splits the input single precision dataset into two half precision sets at the lowest level, uses half precision multiplication, and recombines the result at a later step. This work paves the way for using tensor cores for high precision inputs.

Optimizing the Fast Fourier Transform Using Mixed Precision on Tensor Core Hardware

Different fast Fourier transform (FFT) algorithms for hardware implementation have been considered. We propose an implementation whereby two radix-N1/2passes are carried out in parallel and in which each N1/2-point transform is carried out via a serial input parallel output transform circuit. The processing rate is one clock cycle per input point for the N-point transform regardless of the value of N chosen. The circuit is being implemented with TTL logic and will be used to perform spatial frequency domain filtering on two dimensional infrared camera images in real time; real time meaning processing between frame display.

Implementation of a fast Fourier transform (FFT) for image processing applications

This article describes the implementation of a modular fast Fourier transform (FFT) processor for real-input applications. The nature of the signal has been exploited to reduce to a minimum the number of multiplications and the calculations are performed in an ordered sequence in order to evaluate only the nonredundant terms at each pass. The number of components required for transforming N points is given as a unction of the number of passes. A processing rate of one point per clock cycle at frequencies up to 10 MHz is realizable making the processor ideally suited for a number of real time computations.

On the design of a real time modular FFT processor

A statistical model is used to predict the output signal-to-noise ratio (SNR) when a two-pass fast Fourier transform (FFT) is computed using fixed-point arithmetic. The results show that the ratio varies essentially as the square root of the number of points in the transform. Also included are the results of the simulation of a fixed-point machine and the variation of the error as a function of the length of the coefficients.

https://ieeexplore.ieee.org/iel6/29/26128/01163018.pdf

A two-pass fixed point fast Fourier transform error analysis

For applications requiring high-speed and in-place treatment, it is often advantageous to realize special-purpose computers. This paper describes a discrete Fourier transform (DFT) module for incorpration in fast Fourier transform (FFT) processors. The module is highly suitable for real input applications requiring high-speed transformations. It attributes one point to all frequency channels in one clock cycle. This treatment is not only well suited for the present technology, but appears to be more attractive in view of recent trends in digital circuitry.

Realization of a discrete Fourier transform (DFT) module for incorporation in FFT processors

A&racr-This article describes the implementation of a modular fast Fourier transform (FFT) processor for real-input applications. The nature of the signal has been exploited to reduce to a minimum the number of multiplications and the calculations are performed in an ordered sequence in order to evahrate only the nonredundant terms at each pass. The number ofcomponents required for transforming N points is given as a unction of the number of passes. A processing rate of one point per clock cycle at frequencies up to 10 MHz is realizable making the processor ideally suited for a number of real time computations.

H. Buijs

Papers

Implementation of a fast Fourier transform (FFT) for image processing applications

On the design of a real time modular FFT processor

A two-pass fixed point fast Fourier transform error analysis

Realization of a discrete Fourier transform (DFT) module for incorporation in FFT processors

On The Design of a Real Time Modular