Simple queueing models are used to study the performance tradeoffs of multiple processor systems. Issues considered include the impact of CPU service disciplines and distributions, level of multiprogramming, multitasking, and job priorities.

The impact of distributions and disciplines on multiple processor systems

Until recently, electronically addressable devices such as ferrite core, plated wire, semiconductor memories, and electromechanically addressable devices such as magnetic tapes, disks, and drums were the few technologies from which a computer system designer could build a memory system. A number of different new technologies and devices have been developed that close the "access gap"14between the two dissimilar technologies mentioned above. These include charge-coupled devices (CCD's),2bubble memories,4electron beam addressed memories (EBAM),17and domain tip propagation (DOT).16Other technologies like CMOS1and integrated injection logic (I2L),9compete directly with the existing technologies. Table 1 (see p. 46) shows the possibility of a six-level hierarchy and some cost and performance projections for these technologies.

Cost, Performance, and Size Tradeoffs for Different Levels in a Memory Hierarchy*

The effective use of computer systems for large-scale information management rather than numerical computation is still a largely unsolved problem. In this paper important concepts and theories regarding computer architectures for information management are introduced. The underlying concept, hierarchical decomposition, is presented in the next section.

INFOPLEX: hierarchical decomposition of a large information management system using a microprocessor complex

Due to the linear structure of source text, difficulties may arise in a one-pass compilation process. These difficulties occur when an entity cannot be processed because of a forward reference to information only obtainable from subsequent entities. Classic solutions ask for data structures appropriate for each case. A technique is presented here which uses instead control structures, namely events and processes. The work of the compiler-writer becomes easier both conceptually and in practice because he can forget these problems at the outset and he avoids special processing for each problem. This technique has been applied to the construction of an Algol 68 compiler. Three examples from that implementation are described and discussed here.

An event-driven compiling technique

Anyone concerned with understanding the past, present, and future of high-speed computing must of necessity focus on progress in the components field. He must formulate searching questions about the outlook of that technology and how it affects progress in high-speed computer development.

Special Feature Component Progress: Its Effect on High-Speed Computer Architecture and Machine Organization

In forecasting future types and uses of electronic disks one must consider processing unit architecture and software systems, as well as trends in computer memory technologies. This paper will concentrate on projections of memory technology, including computer architecture and software trends where relevant to these projections. Technologies which have the potential to result in standard commercial products are addressed rather than those which will result only in laboratory prototypes or militarized equipments designed for unique application environments. For example, a technology which may be uniquely suited for space applications may be much too expensive to compete as a commercial product. Bit densities, costs, access times, and other characteristics have been projected as representative of products which are in production, are available in quantity from several vendors, and are therefore competitively priced.

H.D. Frankel

Papers

Electronic Disks in the 1980's