Signal processing application circuits are often implemented following the “system on chip” design methodology. This means that several cooperating subsystems, that are implemented in the same silicon technology, are usually designed and modelled with different approaches and different “abstraction” and detail levels. In this framework, the distinction of what is “analog” and what is “digital” is somehow specious and even useless, and, as a consequence, an extended modelling and simulation environment, suitable for the large class of mixed analog/digital circuits, is desirable. This environment should extend to this class of circuits important simulation tools such as shooting methods for fast steady state computation, periodic small signal and periodic noise analyses, methods that are commonly used when dealing with analog circuits exhibiting periodic behaviors. A possible way to obtain this result is presented in this chapter by resorting to the concept of saltation matrix and extending the variational model to dynamical systems that are not Lipschitz continuous. Theory and applications are presented, also showing glimpses of possible implementation schemes for the proposed modelling and simulation framework.

Steady State Simulation of Mixed Analog/Digital Circuits

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Automatic Reusable Design for Analog Micropower Integrated Circuits

L'expansion du marche des semi-conducteurs dans tous les secteurs d'activite resulte de la capacite de creer de nouvelles applications grâce a l'integration de plus en plus de fonctionnalites sur une surface de plus en plus faible. Pour chaque entreprise, la competitivite depend du cout de fabrication mais aussi de la fiabilite du produit. Ainsi, la phase de test d'un circuit integre, et plus particulierement des circuits analogiques et mixtes, est le facteur predominant dans les choix d'un compromis entre ces deux criteres antagonistes, car son cout est desormais proche du cout de production. Cette tendance contraint les acteurs du marche a mettre en place de nouvelles solutions moins onereuses. Parmi les recherches dans ce domaine, la conception en vue du test (DfT) consiste a integrer pendant le developpement de la puce, une circuiterie additionnelle susceptible d'en faciliter le test, voire d'effectuer un auto-test (BIST). Mais la selection d'une de ces techniques necessite une evaluation de leur capacite de differencier les circuits fonctionnels des circuits defaillants. Ces travaux de recherche introduisent une methodologie d'estimation de la qualite d'une DfT ou d'un BIST dans le flot de conception de circuits analogiques et mixtes. Basee sur la generation d'un large echantillon prenant en compte l'impact des variations d'un procede technologique sur les performances et les mesures de test du circuit, cette methodologie calcule les metriques de test exprimant la capacite de chaque technique de detecter les circuits defaillants sans rejeter des circuits fonctionnels et d'accepter les circuits fonctionnels en rejetant les circuits defaillant. Ensuite, le fonctionnement d'un auto-test numerique adapte aux convertisseurs sigma-delta est presente ainsi qu'une nouvelle methode de generation et d'injection du stimulus de test. La qualite de ces techniques d'auto-test est demontree en utilisant la methodologie d'estimation des metriques de test. Enfin, un demonstrateur developpe sur un circuit programmable demontre la possibilite d'employer une technique d'auto-test dans un systeme de calibrage integre.

Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA

A comprehensive design optimization methodology using intuitive nondimensional parameters of inversion-level and saturation-level is proposed, especially for ultralow-power, low-voltage, and high-performance analog circuits with mixed strong, moderate, and weak inversion metal–oxide–semiconductor transistor (MOST) operations. This methodology is based on the synthesized charge-based MOST model composed of Enz–Krummenacher–Vittoz (EKV) basic concepts and advanced-compact-model (ACM) physics-based equations. The key concept of this methodology is that all circuit and system characteristics are described as some multivariate functions of inversion-level parameters, where the inversion level is used as an independent variable representative of each MOST. The analog circuit design starts from the first step of inversion-level design using universal characteristics expressed by circuit currents and inversion-level parameters without process-dependent parameters, followed by the second step of foundry-process-dependent design and the last step of verification using saturation-level criteria. This methodology also paves the way to an intuitive and comprehensive design approach for many kinds of analog circuit specifications by optimization using inversion-level log-scale diagrams and saturation-level criteria. In this paper, we introduce an example of our design methodology for a two-stage Miller amplifier.

Analog design optimization methodology for ultralow-power circuits using intuitive inversion-level and saturation-level parameters

ADC’s or analog to digital converters are the devices which provide a channel between physical & digital world as they are responsible for converting continuous time analog signal to a digital digit. ADC’s is a prominent component of high speed data communication, signal conditioning & processing applications. So, a power efficientADC is required which will be best suited for these applications. A 4-BIT flash-ADC is simulated in this work in 90 nm CMOS technology. Voltage supply of 0.7 V is applied with 1 μm channel length. Power consumption is then recorded & observed by varying the temperatures at different widths & supply voltages. Minimum power consumption of 11.73 μW at -10degreeCelsius & maximum power consumption of 14.94 μW at 55 degrees Celsius is observed. temperature variation leads to the 25% variations in power consumption. For comparison latest flash-ADC are taken & compared. Comparison shows better performance of this 4-bit flash-ADC from others. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

Power analysis of Flash-ADC in 90nm CMOS Technology

A behavioral model of a 1.8-V, 6-bit flash analog-to-digital converter has been developed based on device parameters using the g/sub m//I/sub d/ methodology. This approach eliminates the need for recharacterization of blocks when device sizes are changed. Furthermore, the performance can be predicted with input only from device and process simulators eliminating the need for a circuit simulator and associated model parameters. Signal to noise plus distortion ratio and differential and integral nonlinearity are predicted and verified at lower resolution with a circuit simulator.

H.-H.P. Shen

Papers

A behavioral model of a 1.8-V flash A/D converter based on device parameters