The most critical constraints in System on chip (SoC’s), to determine the performance are area and power. As technology scales down, innovative clock tree design techniques are required to improve the skew. Hence, skew minimization design should be introduced in VLSI physical design at early stages of SoC’s where it has the highest benefits for QoR. In this paper, skew balance methodology using H-Tree is introduced in Multisource CTS design.

H. H. Surendra

Papers

Skew Analysis on Multisource Clock Tree Synthesis Using H-Tree Structure