A two-dimensional process simulation program has been developed. The process models used for this program are oxidation, diffusion, ion implantation, and deposition/etching of CVD films. The numerical models are based on a finite-difference approximation to diffusion equation. A large number of equations derived from the diffusion equation are solved by Stone's method because of its excellent rate of convergence. Attention is paid primarily to lateral impurity diffusion and lateral oxidation near the edge of the oxidation mask. Oxidation enhanced diffusion of boron is also included. We have obtained good quantitative agreement between calculated and experimentally observed diffused line capacitance variation with reverse bias voltage which is strongly affected by the lateral channel stop diffusion in a locally oxidized process.

Two-dimensional computer simulation models for MOSLSI fabrication processes

Intrinsic capacitance of lightly doped drain (LDD) MOSFET's is measured by means of a four-terminal method without using any on-chip measurement circuits. The gate-to-drain capacitance C gd of LDD MOSFET's is smaller than that of conventional MOSFET's in the saturation region. The technique is applied to determine the effective channel length.

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

A novel approach to device modeling for circuit simulation of integrated circuits is presented. This approach is based on general nonlinear network models in tensor product spline representation. As a consequnce this device modeling approach is technology independent and automatable. Tensor product spline representations of nonlinear branch elements are particularly useful, since the controlling variables are typically directionally dominant and only low rank tensors are needed. The basic properties of splines are reviewed for circuit simulation applications. Device model generation, software implementation, user interfaces and the circuit simulation environment within SPICE are described in detail. Realistic comparisons with conventional device models are given. The approach has been applied to several integrated circuit technologies (1/2-μm silicon MESFET logic, 7-μm CMOS/SOS logic, and 5-μm metal gate bulk silicon CMOS logic). Device models and simulated circuit results are in all cases in excellent agreement with measured device and circuit characteristics. This novel device modeling approach is particularly suitable for circuit design in quickly changing technological environments and for submicron VLSI.

Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies

An on-chip capacitance measurement technique used for interline capacitances has been extended to MOS transistor capacitance measurements. The gate of the test transistor is connected to a reference capacitance made on the same chip. Small ac signals are applied to one of the transistor terminals successively. The magnitude of the ac voltages appearing on the gate node is measured indirectly. C_{gd}, C_{gs} , and C gb are calculated accurately from the measured ac voltage and the reference capacitance value. It was found that C gd and C gs are measured completely free of parasitic capacitances resulting from both the internal on-chip circuit and external wiring. The on-chip circuitry is simple and can easily be scaled down. These features insure this technique is the most suitable for the measurement of minimum, geometry transistors with atto-Farad-range resolution. It is shown that this technique has the ability to detect the capacitance difference which comes from the misalignment of source and drain metal connections. Measurements with this technique are used to first describe the short- and narrow-channel effects on MOS transistor capacitance.

A scaleable technique for the measurement of intrinsic MOS capacitance with atto-Farad resolution

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.

On-chip capacitance measurement circuits in VSLI structures

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively devided a.c. voltage measurement. In test devices, reference and test capacitors are connected in series, and intermidiate node signal is monitored by on chip linear sense amplifier. Utilizing the technique, various capacitances were measured, and quantitativery compared with a two dimensional numerical analysis. The results indicate that the technique is practical and accurate for evaluating capacitive elements in VLSI's.

H. Iwai

Papers

Capacitance measurement technique in high density MOS structures