As the broadband access technologies, such as DSL, cable modem, and gigabit Ethernet, are providing affordable broadband solutions to the Internet from home and the enterprise, it is required to build next generation routers with high-speed interfaces (e.g., 10 or 40 Gb/s) and large switching capacity (e.g., multipetabit). This paper first points out the issues of building such routers, such as memory speed constraint, packet arbitration bottleneck, and interconnection complexity. It then presents several algorithms/architectures to implement IP route lookup, packet classification, and switch fabrics. Some of the functions, such as packet classification, route lookup, and traffic management, can be implemented with emerging network processors that have the advantages of providing flexibility to new applications and protocols, shortening the design cycle and time-to-market, and reducing the implementation cost by avoiding the ASIC approach. Several proposed algorithms for IP route lookup and packet classification are compared in respect to their search/update speeds and storage requirements. Different efficient arbitration schemes for output port contention resolution are presented and analyzed. The paper also surveys various switch architectures of commercial routers and switch chip sets. At the end, it outlines several challenging issues that remain to be researched for next generation routers.

Next generation routers

A system for controlling the flow of data cells through a packet switch combines both input and output buffers in a feedback loop. The fullness level of output buffers is continuously monitored and reported to an access device on the input side of the switch. The access device includes input buffers and a throttling device to stop the flow of data cells, and hold them in the input buffers, when the fullness level of the output buffers exceeds a predetermined level. A status message of output buffers fullness is compared to an access message indicating which output buffers are addressed by cells in the input buffers, and only those cells addressed to overfull output buffers are stopped by the throttling device.

Flow control system for packet switches

The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

/pdf/architectural-choices-in-large-scale-atm-switches-4pi0tpyd2l.pdf

Architectural choices in large scale ATM switches

A multicast switch for routing incoming cells having a multicast bit pattern and a priority value, arriving at a plurality of input ports, to one of a plurality of output ports, which includes input port controllers and routing modules. Each of the routing modules routes received cells to an associated one of a plurality of groups of output ports and provides a feedback priority value based on a priority value associated with a lowest priority cell passed to the associated group of output ports. Each of the input port controllers receives the incoming cells, buffers a head-of-line cell, transmits the head-of-line cell to each of the routing modules, stores the multicast bit pattern, compares the priority value of the buffered head-of-line cell with the feedback priority values from each of the routing modules to form a set of comparison values, updates the multicast bit pattern based on the comparison values to form an updated multicast bit pattern, and either retransmits the buffered head-of-line cell, or buffers and transmits a next cell, based on the updated multicast bit pattern.

Scaleable multicast ATM switch

Asynchronous transfer mode (ATM) technology is discussed in relation to the requirements of corporate networking. An introduction to ATM switch architecture is presented. The various approaches to ATM switch design that have appeared in previously published literature are reviewed. A discussion is presented of some current issues facing the development of the ATM networks. It is argued that much simpler solutions to many of these issues may be adopted in the context of the corporate network than is permissible for the public broadband network. >

ATM technology for corporate networks

The author proposes a recursive modular architecture for a very large scale asynchronous transfer mode (ATM) switch. By extending the concept of the original knockout switch, the cell filtering and contention resolution functions are distributed over many small switch elements, which are arranged in a crossbar structure. The output ports of a switch fabric are partitioned into a number of groups by a novel grouping network to permit sharing of the routing paths in the same group. This partitioning and sharing concept is applied recursively to construct the entire switch elements. The technique of channel grouping for trunk circuits can be incorporated in the proposed ATM switch to improve the cell loss/delay performance while the cells' sequences are retained. A prototype circuit for the key switch element has been designed, and it has been shown that more than 4000 of the switch elements can be integrated into a VLSI chip with existing CMOS 1- mu m technology. >

H.J. Chao

Papers

A recursive modular terabit/second ATM switch