A method for accessing a signal value of an FPGA (5) at runtime, including the steps of loading an FPGA hardware configuration (24) into the FPGA (5), executing the FPGA hardware configuration (24) in the FPGA (5), requesting a signal value of the FPGA (5), sending status data from a functional level (6) of the FPGA (5) to a configuration memory (8) in its configuration level (7), reading the status data from the configuration memory (8) as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model (20), using a hardware description language, including the steps of creating an FPGA hardware configuration (24), identifying memory locations (9) of a configuration memory (8) for status data of at least one signal value based on the FPGA hardware configuration (24), and creating a list with signal values accessible at runtime and the memory locations (9) corresponding thereto.

H·卡尔特

Papers

Random access to signal values of an FPGA at runtime