An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The direct injection-locking scheme features wide locking ranges, a very low input capacitance, and highest frequency capability. The direct locking and the tradeoff between power consumption and tank quality factor is verified through three test circuits in 0.13-/spl mu/m standard CMOS, aiming at input frequency ranges of 50, 40, and 15 GHz. The 40- and 50-GHz dividers consume 3 mW with locking ranges of 80 MHz and 1.5 GHz. The 15-GHz divider consumes 23 mW and features a locking range of 2.8 GHz.

A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider

Injection-locked frequency dividers (ILFDs) are versatile analog circuit blocks used, for example, within phase-locked loops (PLLs). An important attribute is substantially lower power consumption relative to their digital counterparts. The model described in this paper unifies the treatment of injection-locked and regenerative systems. It also provides useful design insights by clarifying the nature and role of the nonlinearity present in many mixer-based frequency conversion circuits. The utility of the model is demonstrated in the calculation of both the steady-state and dynamic properties of ILFD systems, and the subsequent computation of the corresponding phase noise spectrum. Illustrative circuit examples show close correspondence between theory and simulation. Finally, measurement results from a 5.4-GHz divide-by-2 ILFD fabricated in 0.24-/spl mu/m CMOS show close correspondence between experiment and theory.

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A unified model for injection-locked frequency dividers

In this paper, the locking range of the injection-locked ring oscillators is investigated. To improve the injection efficiency and the locking range for superharmonic frequency division, a multiple-injection technique is proposed. Using a 0.18-mum CMOS process, a wideband frequency divider based on a three-stage ring oscillator is implemented for demonstration. With a tunable free-running frequency, the fabricated circuit provides 2:1 and 4:1 frequency division with a single-ended input signal ranging from 13 to 25 and 30 to 45 GHz, respectively. Compared with the case of the single-ended injection, the locking range of the frequency divider almost doubles when multiple-input injection with optimum phases is utilized. The experimental results exhibit good agreement with the theoretical derivation and the circuit simulation.

Analysis and Design of Wideband Injection-Locked Ring Oscillators With Multiple-Input Injection

Injection-locked oscillators divide at very high frequencies and consume low power. They are not widely deployed in commercial products because they operate over small, often unpredictable, ranges of input frequencies. Ring oscillators as dividers are interesting because they are compact, and capable of a multi-phase output, including quadrature phases. Using a generalized Adler's equation for large injections, we analyze the operation of injection-locked ring oscillators and derive expressions for the input lock range. We discover that injection in the correct progressive phases greatly widens the lock range; all that is needed is the right delay cell circuit, and the injection input in one or two phases. As proof of concept, divide-by-two and six prototypes are built. The measured lock range spans DC to 1.5 the free-running frequency, the highest reported to date.

Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers

We implemented prescalers that can operate up to 2.8-GHz by exploiting the injection locking phenomena in differential CMOS ring oscillators. We tested a 5-stage, 1-GHz injection-locked modulo-8 prescaler fabricated in a 0.24-/spl mu/m CMOS technology that consumes 350 /spl mu/W of power and occupies 0.012 mm/sup 2/ of die area. The locking range is 20 MHz and the locked phase noise is -110 dBc/Hz @ 100 kHz. A 2.8-GHz, 3-stage, modulo-4 divider is also presented.

H. Wu

Papers

A 19GHz 0.5mW 0.35mm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement