This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The transceiver has been fabricated in a standard 65-nm CMOS process. It in cludes a receiver with a 17.3-dB conversion gain and less than 8.0-dB noise figure, a transmitter with a 18.3-dB conversion gain, a 9.5-dBm output 1 dB compression point, a 10.9-dBm saturation output power and 8.8-% power added efficiency. The 60-GHz frequency synthesizer is implemented by a combination of a 20-GHz PLL and a 60-GHz quadrature injection-locked oscillator, which achieves a phase noise of -95 dBc/Hz@l MHz-offset at 60 GHz. The transceiver realizes IEEE802.15.3c full-rate wireless communication for all 16QAM/8PSK/QPSK/BPSK modes, and the communication distances with the full data rate using 2.16-GHz bandwidth, measured with an antenna built in the package, are 2.7-m (BPSK/QPSK) and 0.2-m (8PSK/16QAM). The measured maximum data rates are 8 Gb/s in QPSK mode and 11 Gb/s in 16QAM mode over a 5 cm wireless link within a bit error rate (BER) of <;10-3. The transceiver consumes 186 mW from a 1.2-V supply voltage while transmitting and 106 mW from 1.0-V supply voltage while receiving. Both transmitter and receiver are driven by a 20-GHz PLL, which consumes 66 mW, including output buffer, from a 1.2-V supply voltage.

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c

This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can be extended up to 10 Gb/s. The 40-nm CMOS baseband including analog, digital, and I/O consumes 196 and 427 mW for 16QAM in transmitting and receiving modes, respectively. In the analog baseband, a 5-b 2304-MS/s ADC consumes 12 mW, and a 6-b 3456-MS/s DAC consumes 11 mW. In the digital baseband integrating all PHY functions, a (1440, 1344) LDPC decoder consumes 74 mW with the low energy efficiency of 11.8 pJ/b. The entire system including both RF and BB using a 6-dBi antenna built in the organic package can transmit 3.1 Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

This paper presents a 10 Gbps millimeter wave OFDM experimental system using a highly efficient modulation and coding scheme where iterative phase noise compensation can drastically alleviate performance degradation due to phase noise. 60 GHz frequency synthesizer in a silicon RF-CMOS IC suffers from relatively large phase noise, which severely degrades the performance of the 10 Gbps OFDM using 64QAM and LDPC code with coding rate of 14/15. In order to alleviate this impairment, the experimental system applies combination of decision-directed phase noise compensation (DD-PNC), decision-directed channel estimation (DDCE) and packet interleaving (P-IL) to OFDM reception processing. The sophisticated combination of iterative processing provides a synergistic effect on coping with the influence of the phase noise by exploiting outputs of the LDPC decoder. Experimental results of the 10 Gbps OFDM with 60 GHz cable connection demonstrate that the combination can achieve 10 Gbps throughput at SNR of 25.8 dB when the phase noise level is -89 dBc/Hz at 1 MHz offset.

10 Gbps millimeter-wave OFDM experimental system with iterative phase noise compensation

A novel compact-range wireless access system is proposed for multi-Gb/s data transfer in the 60-GHz band. Large-array antennas in the access point generate a quasi-plane wave and form a stable communication zone proportional to the antenna size. The link budget based upon the Friis transmission equation is not applicable as ever in this compact-range communication system. The signal coverage up to 10 m still falls within the Fresnel region of the large-array antenna. Mobile users everywhere within the coverage receive almost constant field strength free of multipath interference. To demonstrate the viability, circularly polarized waveguide slot arrays of various sizes are designed and fabricated. After the evaluation of conventional antenna radio frequency (RF) performance, bit-error rate (BER) and signal-to-noise ratio (SNR) measurements are conducted to evaluate the prototype of a compact-range Gigabit wireless access system.

A 60-GHz Band Compact-Range Gigabit Wireless Access System Using Large Array Antennas

We report the development of the prototype of a high-speed wireless file-transfer system using a 60-GHz band The prototype achieved an effective user-data rate over 3 Gb/s using a quadrature-phase-shift keying modulation, including overheads of a physical layer and a retransmission control between two memory devices, by using a new 40-nm CMOS baseband LSI and automatic direct memory-access control

Prototype of 3-Gb/s 60-GHz millimeter-wave-based wireless file-transfer system

High throughput architecture of an encoder and a decoder for a quasi-cyclic low-density parity-check (LDPC) code is proposed. A new systematic encoding method is carried out by polynomial manipulation. The proposed decoder architecture, where the check-node process is split into two processes so that the memory access becomes column-wise, enables overlapped message-passing for any parity-check matrix. The hardware architecture for the check-node processes utilizing a quasi-cyclic structure does not require complex multiplexers. Hardware employing the proposed architecture for a (1440,1344) LDPC code designed for high throughput millimeter wave application is evaluated using 65 nm CMOS technology. The gate count of the encoder for 3 Gbps and 6 Gbps throughput is 2.5 k and 3.1 k, respectively, and the gate count of the decoder for 8 iterations is 304 k and 409 k, respectively. A bit-error rate of 10-6 is obtained at Eb/N0 of 5.9 dB, and the estimated power consumption of the decoder is 58 mW for 3 Gbps and 86 mW for 6 Gbps.

H. Yamagishi

Papers

High throughput hardware architecture for (1440,1344) low-density parity-check code utilizing quasi-cyclic structure