The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms. >

CORDIC-based VLSI architectures for digital signal processing

A detailed analysis of the quantization error encountered in the CORDIC (coordinate rotation digital computer) algorithm is presented. Two types of quantization error are examined: an approximation error due to the quantized representation of rotation angles, and a rounding error due to the finite precision representation in both fixed-point and floating-point arithmetic. Tight error bounds for these two types of error are derived. The rounding error due to a scaling (normalization) operation in the CORDIC algorithm is also discussed. An expression for overall quantization error is derived, and several simulation examples are presented. >

The quantization effects of the CORDIC algorithm

The coordinate rotation digital computer (CORDIC), an iterative arithmetic algorithm for computing generalized vector rotations without performing multiplications, is discussed. For applications where the angle of rotation is known in advance, a method to speed up the execution of the CORDIC algorithm by reducing the total number of iterations is presented. This is accomplished by using a technique called angle recoding, which encodes the desired rotation angle as a linear combination of very few elementary rotation angles. Each of these elementary rotation angles takes one CORDIC iteration to compute. The fewer the number of elementary rotation angles, the fewer the number of iterations are required. A greedy algorithm which takes only O(n/sup 2/) operations is developed to perform CORDIC angle recoding. It is proven that this algorithm is able to reduce the total number of required elementary rotation angles by at least 50% without affecting the computational accuracy. >

An angle recoding method for CORDIC algorithm implementation

The coordinate rotation digital computer (CORDIC) algorithm is used in numerous special-purpose systems for real-time signal processing applications. An analysis of fixed-point CORDIC in the Y-reduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. The authors describe two approaches for tackling the numerical accuracy problem. The first approach builds on a fixed-point CORDIC unit and eliminates the problem by including additional hardware for normalization. A method for integrating the normalization operation with the CORDIC iterations for efficient implementation in O(n/sup 1.5/) hardware is provided. The second solution to the accuracy problem is to use a floating-point CORDIC unit but reduce the implementation complexity by using a hybrid architecture. Arguments to support the use of such an architecture in certain special-purpose arrays are presented. >

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Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors

This paper proposes a low complexity n-dimensional (nD) FastICA algorithm and architecture by introducing the concept of coordinate rotation where n ≥ 2. The proposed algorithm can merge the two key steps of conventional FastICA-preprocessing and update and is therefore capable of reducing the hardware complexity of the conventional FastICA significantly as demonstrated in this paper. Hardware implementation can further be simplified due to the recursive nature of the proposed algorithm where the same 2D hardware module can be used as the fundamental core to implement nD architecture. Together with the algorithm formulation, its functionality is also validated and hardware complexity is analyzed and compared with the conventional nD FastICA.

Coordinate Rotation Based Low Complexity N-D FastICA Algorithm and Architecture

In this paper, we present a doubly pipelined VLSI Cordic array processor for digital signal processing computations The basic notion of doubly pipelined CORDIC computation will be introduced first Then, some potential applications to digital signal processing problems will be discussed Specifically, we shall demonstrate how a doubly pipelined CORDIC processor array can be applied to compute discrete Fourier transform and Fast Fourier transform, to implement Lattice filters, to solve Toeplitz systems as well as matrix QR factorizations It is shown that by adopting a secondary pipelining, about one third hardware can be saved, and sometimes the throughput of the entire CORDIC processor array may be doubled

H. Yu

Papers

Doubly pipelined Cordic array for digital signal processing algorithms