A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips.

Memory Module, Cache System and Address Conversion Method

Methods and systems for conserving power using predictive models and signaling are described Parameters of a power management policy are set based on predictions based on user activity and/or signals received from a remote computer which define a user preference In an embodiment, the power management policy involves putting the computer into a sleep state and periodically waking it up On waking, the computer determines whether to remain awake or to return to the sleep state dependent upon the output of a predictive model or signals that encode whether a remote user has requested that computer remain awake Before returning to the sleep state, a wake-up timer is set and this timer triggers the computer to subsequently wake-up The length of time that the timer is set to may depend on factors such as the request from the remote user, context sensors and usage data

Conserving power using predictive modelling and signaling

A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Memory system supporting nonvolatile physical memory

One embodiment of the present invention includes a method for enabling a client node to automatically read ahead data from a network based file system. Specifically, in response to an application operating on the client node requesting a data page, the client node requests delivery of data pages from the network based file system. Upon reception, these data pages can each be served to the application. After each data page is served, it is determined whether the number of unrequested available data pages is less than the value of M. If so, an asynchronous read-ahead request is sent to a primary node of the network based file system for P number of data pages. The values of M and P can be such that P data pages can be fetched before M data pages are consumed by the requesting application.

Read ahead technique for network based file systems

A method includes identifying a set of instructions to be executed as a transaction that is to access a section of memory, prior to executing the set of instructions as the transaction, facilitating a non-speculative access to a data cache, the data cache comprising a plurality of cache lines, each cache line comprising a lock to lock a respective portion of the memory, determining if the section of memory is available for the transaction in view of locks of the plurality of cache lines, and in response to a determination that the section of memory is not available, causing the non-speculative access to the data cache to be repeated.

Using nonspeculative operations for lock elision

A memory storage system includes a line cache including a plurality of pages. A first central processing unit (CPU) accesses data stored in the pages of the line cache. A first memory device stores data that is loaded into the line cache when a miss occurs. After an initial miss, the line cache prevents additional misses as long as the first CPU is addressing sequential memory locations of the first memory device. When the miss occurs, n pages of the line cache are loaded with data from sequential locations in the first memory device, wherein n is greater than one. When the CPU requests data from an m th page of the n pages in the line cache, wherein m is greater than one and less than or equal to n, the line cache loads p additional pages with data from sequential locations in the first memory device.

Hai-Hoa Van

Papers

Line cache controller with lookahead