Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.

Semiconductor processing system and methods using capacitively coupled plasma

An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Semiconductor processing systems having multiple plasma configurations

A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

A method of selectively etching a metal-containing film from a substrate comprising a metal-containing layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions, and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the metal-containing layer at a higher etch rate than the reactive gas etches the silicon oxide layer.

Methods for etch of metal and metal-oxide films

A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.

Methods for etch of sin films

A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r 1 of the sacrificial oxide film is higher than an etching rate r 2 of the buried oxide layer during the etching.

Manufacturing method of fin-type field effect transistor

A switch device used in a crossbar memory array having a non-volatile memory includes: a laminated body formed of a semiconductor film and an insulating film laminated on the semiconductor film; and a pair of electrode layers having the laminated body therebetween. The semiconductor film is made of a semiconductor material having an I-V characteristic with a negative resistance region.

Switch device and crossbar memory array using same

PROBLEM TO BE SOLVED: To provide a switch element that exhibits low on-resistance and has a high on/off resistance ratio, high operating speed, a relatively high threshold voltage for turning on, and high withstand voltage, and to provide a crossbar memory array using the same.SOLUTION: A switch element 10 used for a crossbar memory array having a nonvolatile memory comprises: a stack 3 formed by stacking a semiconductor film 1 composed of a semiconductor material in which the IV characteristics has a negative resistance region and an insulating film 2; and a pair of electrode layers 4 and 5 formed so as to sandwich the stack 3.

Switch element and crossbar memory array using the same

PROBLEM TO BE SOLVED: To provide a method by which a fin type field effect transistor wherein constriction is suppressed can be easily and surely manufactured by using an SOI wafer. SOLUTION: An SOI wafer is used to selectively dry-etch a single crystal silicon layer 3 until an embedded oxide layer 2 as a base is exposed and to form a fin-like projection 5. The surface of the projection including damage thereon is oxidized to form a sacrifice oxide film 6, and the sacrifice oxide film 6 is removed by etching, so as to form a film having a clean surface. In this case of manufacturing such the fin type field effect transistor, the etching rate (r 1 ) of the sacrifice oxide film 6 is made higher than that (r 2 ) of the embedded oxide layer 2. COPYRIGHT: (C)2008,JPO&INPIT

Method of manufacturing fin type field effect transistor

A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.

Hajime Nakabayashi

Papers

Manufacturing method of fin-type field effect transistor

Switch device and crossbar memory array using same

Switch element and crossbar memory array using the same

Method of manufacturing fin type field effect transistor

Phase change memory and method for fabricating phase change memory