: This thesis is concerned with the development of a model to analyze a Digital Image Synthesizer (DIS) integrated circuit designed to create false target images to deceive Inverse Synthetic Aperture Radar (ISAR). The DIS is able to recreate the scattering effect of a moving target by using appropriate phase and gain modulations on an intercepted ISAR chirp signal before retransmitting it with the proper time delay. The DIS signal processing and the ISAR compression of the modulated return are modeled to examine the range-Doppler profile of a synthesized false target image. The image is representative of the image that would appear on an ISAR display. ISAR image quality is used to evaluate different DIS architectures and bit formats. Evaluation of the image quality is based on the deviation from an infinite resolution false target image. The results obtained from evaluating different DIS architectures indicate that the design is tolerant of significant quantization errors. The model is used to validate the architecture of the integrated circuit being fabricated. Finally, various different ISAR integration times and pulse repetition frequencies are used to confirm the integrity of the model.

Performance Analysis of a Digital Image Synthesizer as a Counter-Measure Against Inverse Synthetic Aperture Radar

: This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is mainly used against Inverse Synthetic Aperture Radars as an electronic counter measure. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated in Aldec Active HDL(TM), Simulation results were compared with C++ and Matlab simulation results for verification. Main subcomponents, a single Range Bin Processor (RBP), a cascade of 4 RBP 5 and a cascade of 16 RBP 5 were tested and verified. The overhead control circuitry, including Self Test Circuitry and Phase Extractor, was tested separately. Finally, the overall DIS was tested and verified using the control circuitry and a cascade of 4 RBP 5 together, representing the actual 512 RBP 5. As a result of this research, the majority of the DIS was functionally tested and verified.

VHDL modeling and simulation of a digital image synthesizer for countering ISAR

Abstract : The subject of this thesis is to model and verify the correctness of the architecture of the Digital Image Synthesizer (DIS) The DIS, a system-on-a-chip, is especially useful as a counter-targeting repeater. It synthesizes the characteristic echo signature of a pre- selected target. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated. Different software oriented verification approaches were researched and a White-box approach to functional verification was adopted. An algorithm based on the hardware functionality was developed to compare expected and simulated results, Initially, the architecture of one Range Bin Modulator was exported. Modifications to the VHDL source code included modeling of the behavior of the N-FET and P-FET transistors as well as Ground and Vdd (the voltages connected to the drains of the FETs). It also included renaming of entities to comply with VHDL naming conventions. Simulation results were compared to manual calculations and Matlab programs to verify the architecture. The procedure was repeated for the architecture of an Eight-Range Bin Modulator with equally successful results. VHDL was then used to create a super class of a 32-Range Bin Modulator. Test vectors developed in Matlab were used to yet again verify correct functionality.

https://calhoun.nps.edu/bitstream/10945/9795/3/02Sep%255FBergon.pdf

Hakan Bergon

Papers

VHDL modeling and simulation for a digital target imaging architecture for multiple large targets generation