In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.

Line-timing in packet-based networks

PURPOSE:To supply a stable master clock signal with high reliability by detecting an abnormality of the phase of a reference clock signal before it has a considerable influence upon a generated master clock signal and switching this clock signal to a new reference clock signal CONSTITUTION:In comparison with a selectivity Qe of a resonance circuit for extracting clock components included in a clock extracting circuit 1 of each system, an equivalent Qp of a phase locked oscillator PLO51 included in a master clock generaging circuit 5 is set to a sufficiently higher value For example, if an abnormal situation such as loss of a transmission signal in the reference side is caused, the speed of phase changed of the master clock signal generated from the oscillator PLO51 is made sufficiently lower than that of the clock signal of the clock extracting circuit 1 in the loss side, and the abnormality of the reference signal is detected by the phase difference between them exceeding a specific threshold, and the reference signal is switched to the reference signal of the other side where no abnormalities are detected in phase difference Thus, variance of the phase of the master clock signal for the occurrence of an abnormal situation is held down to a minimum

Hamada Tatsuyoshi

Papers

Clock signal selecting system