Provided are a semiconductor device that optimizes the operation characteristics such as of both an insulating gate type transistor for high voltage and an insulating gate type transistor for low voltage, and a method of manufacturing the same. Specifically, a patterned resist ( 25 ) is formed so as to cover a low voltage operation region (A 2 ), a second LDD implantation process of implanting an impurity ion ( 14 ) by using the resist ( 25 ) as a mask, is performed over a silicon oxide film ( 6 ) thereby to form an impurity diffusion region ( 13 ) in the surface of a semiconductor substrate ( 1 ) in a high voltage operation region (A 1 ). After this step, the silicon oxide film ( 6 ) in the high voltage operation region (A 1 ) contains the impurity during the second LDD implantation process whereas the silicon oxide film ( 6 ) in a low voltage operation region (A 2 ) contains no impurity. This leads to such a characteristic that in the following pre-treatment with a wet process, the silicon oxide film ( 6 ) containing the impurity in the high voltage operation region (A 1 ) is reduced in thickness, and the silicon oxide film ( 6 ) containing no impurity in the low voltage operation region (A 2 ) is not reduced in thickness.

Semiconductor device and method of manufacturing same

A radio frequency ('RF') (100) circuit configured in accordance with an embodiment of the invention is fabricated on a substrate using integrated passive device ('IPD') process technology. The RF circuit (100) (which may be, for example, a harmonic filter) includes at least one RF signal line section (204) and an integrated RF coupler (304) located proximate to the RF signal line section. The integrated RF coupler (304), its output (212) and grounding contact pads (210), and its matching network (208) are fabricated on the same substrate using the same IPD process technology. The integrated RF coupler provides efficient and reproducible RF coupling without increasing the die footprint of the RF circuit.

Radio frequency circuit with integrated on-chip radio frequency signal coupler

The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.

Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity

A plurality of devices, such as devices that are utilized for implementing radio frequency applications, can be formed in the same substrate. Each of these devices may be formed over a triple well that includes at least one well capable of being biased. Each of the wells is coupled to a well bias through a resistor. In some embodiments, a plurality of wells operating at a relatively high frequency may be connected to the same bias potential, each through separate resistors. The noise coupling may be reduced through the use of the bias resistors.

Integrated radio-frequency circuits

An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor's performance and may provide better structural support.

Integrated inductive circuits

A monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), a polysilicon resistor (58), and an inductor (155), and an ESD protection device (160). A first P+ sinker (28) provides signal isolation between two FETs (113, 115) separated by the first sinker (28) and is coupled to a source region (86) of a power FET (115) via a self-aligned titanium silicide structure (96). A second P+ sinker (29) is coupled to a bottom plate (44) of the double polysilicon capacitor (57). A third P+ sinker (178) is coupled to a source region (168) of the ESD protection device (160) via another titanium silicide structure (174).

Han-Bin Kuo Liang

Papers

Monolithic RF mixed signal IC with power amplification