A gateway for screening packets transferred over a network. The gateway includes a plurality of network interfaces, a memory and a memory controller. Each network interface receives and forwards messages from a network through the gateway. The memory temporarily stores packets received from a network. The memory controller couples each of the network interfaces and is configured to coordinate the transfer of received packets to and from the memory using a memory bus. The gateway includes a firewall engine coupled to the memory bus. The firewall engine is operable to retrieve packets from the memory and screen each packet prior to forwarding a given packet through the gateway and out an appropriate network interface. A local bus is coupled between the firewall engine and the memory providing a second path for retrieving packets from memory when the memory bus is busy.

Firewall including local bus

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

The present invention relates to a method, apparatus and system for managing virtual memory, in which a co-processor ( 224 ) is adapted to use virtual memory with a host processor ( 202 ). A host memory ( 203 ) is coupled to the host processor ( 202 ) to implement the virtual memory. The co-processor ( 224 ) includes a virtual-physical memory mapping device ( 915 ) for interrogating a virtual memory table and for mapping one or more virtual memory addresses ( 880 ) requested by the co-processor ( 224 ) into corresponding physical addresses ( 873 ) in the host memory ( 203 ). The virtual memory table is stored in two or more non-contiguously addressable regions of the host memory ( 203 ), and is preferably a page table. The memory mapping device ( 915 ) further includes a multiple-entry translation lookaside buffer ( 889 ) for caching virtual-to-physical address mappings ( 872 ), where entries in the buffer ( 889 ) are replaced on a least recently used replacement basis. The memory mapping device ( 915 ) also includes devices ( 901 ) for comparing, replacing, singly invalidating and multiply invalidating one or more entries of the translation lookaside buffer ( 889 ). It also includes a hashing device ( 892 ) for, upon an occurrence of a miss in the translation lookaside buffer ( 889 ), hashing a virtual memory address ( 880 ) using a hash function to produce an index into the virtual memory table.

Method, apparatus and system for managing virtual memory with virtual-physical mapping

An apparatus for providing a number of ports with burst access to a DRAM array includes a memory array, a controller for controlling the memory array, a write device for writing to the memory array, a read device for reading from the memory array, a FIFO output buffer for temporarily storing data read from the memory array and/or a FIFO input buffer for temporarily storing data prior to writing to the memory array.

Memory controller architecture

A novel structure for a highly-scaleable high-performance shared-memory computer system having simplified manufacturability. The computer system contains a repetition of system cells, in which each cell is comprised of a processor chip and a memory subset (having memory chips such as DRAMs or SRAMs) connected to the processor chip by a local memory bus. A unique type of intra-nodal busing connects each system cell in each node to each other cell in the same node. The memory subsets in the different cells need not have equal sizes, and the different nodes need not have the same number of cells. Each node has a nodal cache, a nodal directory and nodal electronic switches to manage all transfers and data coherence among all cells in the same node and in different nodes. The collection of all memory subsets in the computer system comprises the system shared memory, in which data stored in any memory subset is accessible to the processors on the other processor chips in the system. Each location in the system shared memory has a unique real address, which may be used by any processor in the system. Thus, the same memory addresses may be used in the executable instructions of all processors in the system. The nodal directories automatically manage the coherence of all data being changed in all processor caches in the computer system, regardless of where the data is stored in the shared memory of the system and regardless of which cell in the system contains the processor changing the data to provide data coherence across all nodes in the computer system.

Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls

A microprocessor has a CPU, cache memories including TLBs, an internal memory control section (IMC) for controlling the data access operation to the cache memories, an external bus controller for controlling the data input/output operation between external memories and the cache memories, a first group of internal buses for connecting the CPU, the cache memories and IMC, and for transferring logical addresses, logical data and data among the CPU and the cache memories, and a second group of internal buses for connecting the cache memories, IMC and the external bus controller, and for transferring data among the cache memories and the external memories. Each cache memory and IMC are connected to the first group of internal buses and to the second group of internal buses in parallel, and the IMC controls the use of the second group of internal buses, and the data input/output operation to the group of the internal memories.

Harutaka Goto

Papers

Microprocessor with two groups of internal buses