Showing papers by "Heinrich Meyr published in 2000"

Retargetable compiled simulation of embedded processors using a machine description language

Abstract: Fast processor simulators are needed for the software development of embedded processors, for HW/SW cosimulation systems, and for profiling and design of application-specific processors. Such fast simulators can be generated based on the machine description language LISA. Using this language to model processor architectures enables the generation of compiled simulators on various abstraction levels, assemblers, and compiler back ends. The article discusses the requirements of software development tools on processor models and presents the approach based on the LISA language. Furthermore, the implementation of a retargetable environment consisting of compiled simulator, debugger, and assembler is presented. Measurements for a verified, cycle-based LISA model of the TI TMS320C62× DSP show that that this approach achieves between 37× and 170× higher simulation speed compared to a commercial simulator using a standard technique and the same accuracy level.

Retargeting of compiled simulators for digital signal processors using a machine description language

Abstract: This paper presents a methodology to retarget the technique of compiled simulation for digital signal processors (DSPs) using the modeling language LISA. In the past, the principle of compiled simulation as means for speeding up simulators has only been implemented for specific DSP architectures. The new approach presented here discusses methods of integrating compiled simulation techniques to retargetable simulation tools. The principle and the implementation are discussed in this paper and results for the TI TMS320C6201 DSP are presented.

Performance analysis of phasor estimation algorithms for a FDD-UMTS RAKE receiver

Abstract: The performance of phasor estimation algorithms for the UMTS RAKE receiver are analysed. Due to the need of covering a wide range of possible mobile speeds and spreading factors, two different algorithms are considered, namely a LMS-Kalman type algorithm, and a Wiener filter. The Wiener filter is considered both, as a predictor and a smother. It is shown that the simpler LMS-Kalman predictor is particularly suited for low mobile speeds and low spreading factors, whereas higher speeds and/or higher spreading factors require the usage of the more complex Wiener filter. Furthermore, the very high spreading factors (128-512) require the usage of the common pilot channel in order to facilitate smoothing instead of prediction.

Efficient building block based RTL code generation from synchronous data f-low graphs

Abstract: This paper presents a RTL-HDL code generation from synchronous data-flow graphs which supports the building block based design of data-flow oriented ASIC systems. Here, additional interfacing and controlling hardware is generated to adapt non-matching interfacing properties. In order to reduce interface register cost, a retiming approach is taken to schedule optimum building block activation times. The code generation methodology is compared to an existing approach using different case studies.

Low complexity adaptive code tracking with improved multipath resolution for DS-CDMA communications over fading channels

Abstract: A new adaptive timing error detector (TED) embedded in a code-tracking loop for RAKE reception of direct sequence-CDMA signals is presented. The loop consists of a digital coherent TED and a loop filter with lowpass characteristic. In a multipath fading environment, one such loop can be allocated for each finger in a RAKE receiver and the interference from adjacent paths can be mitigated by adaptively prefiltering the signal prior to the correlation process. The filter coefficients are computed online in order to minimize an interference cost function. Multipaths whose delays differ by as little as one chip duration become resolvable and can be tracked, resulting in significant performance gains of the overall system, especially if the channel delay spread is small. The tracking performance of the proposed loop is assessed by computer simulation.

ICORE: a low-power application specific instruction set processor for DVB-T acquisition and tracking

Abstract: A design methodology is presented to optimize application specific instruction set processors (ASIPs) with respect to performance and power. The methodology uses semi-custom design with incremental datapath and instruction set enhancements of a conventional, unoptimized architecture. ICORE, a low-power ASIP for DVBT acquisition and tracking algorithms, demonstrates the huge potential concerning power savings of these optimizations.

Multipath resistant coherent timing error detector for DS-CDMA applications

Abstract: A new coherent timing error detector (TED) for timing/code tracking loops used inside RAKE receivers in CDMA systems is presented. In contrast to the conventional TED it is well suited for the case of multipath propagation channels. In order to accomplish this task a compensation term is introduced inside the tracking loop directly behind the conventional TED. This compensation term is calculated using the knowledge on the relative delays of all paths and their respective channel coefficients. A compensation scheme like the one described here becomes necessary whenever closely spaced paths have to be tracked. This fact makes this algorithm a favorable candidate for indoor scenarios where individual paths can be spaced even more closely than one chip. The performance of the presented scheme is assessed by means of simulation.

Increasing the power efficiency of application specific instruction set processors using datapath optimization

Abstract: Application specific instruction set processors (ASIPs) can be optimized both for speed and power taking advantage of the flexibility of a synthesized semi-custom implementation. The current case study evaluates the effect of datapath and instruction set optimisation using two examples from terrestrial digital video broadcasting (DVB-T) acquisition and tracking algorithms. Starting from a conventional, unoptimized instruction set architecture, which uses simple instructions like any commercially available DSP, incremental application specific optimizations are performed. Results in terms of cycle count and energy per task are used to evaluate the feasibility and the power efficiency of each implementation. The results show a huge potential (>6x) concerning power savings using this design methodology.

DSP core verification using automatic test case generation

Abstract: The verification methodology for a TMS320C25 compatible embedded DSP core is described. The DSP core has been implemented in synthesizable VHDL and has been cosimulated with the original DSP to verify correct behavior. Automatic test case generation together with hand-crafted code has been used as a means of providing stimuli to achieve increased RTL-simulation coverage. The cosimulation environment for this verification and the process of automatic test case generation is described in detail. Experimental results in terms of simulation coverage are discussed. Finally, a classification of all identified design flaws in the implementation is given and error-prone parts of the HDL design are identified.