An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A light-emitting device package including: a package main body including a cavity and a lead frame including a mounting portion disposed in the cavity and a plurality of terminal portions; a light-emitting device chip mounted on the mounting portion; a plurality of bonding wires for electrically connecting the plurality of terminal portions and the light-emitting device chip; a light-transmitting encapsulation layer filled in the cavity; and a light-transmitting cap member disposed in the cavity and blocking the encapsulation layer to contact the plurality of bonding wires.

Light emitting device package

A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Microelectronic packages and methods therefor

An apparatus for use in decoding a bar code symbol includes a first integrated circuit chip with a wafer level camera, at least one light source, and a plurality of contact pads on a surface of the chip and a second integrated circuit chip with a processor, memory, plurality of contact pads on a surface of the chip, and plurality of contact pads on another surface of the chip. The apparatus includes a PCB having a plurality of contact pads disposed on at least one surface of the PCB and wherein the first and second integrated circuit chips are vertically stacked on the PCB and the plurality of contact pads on the first and second integrated circuit chips interface with the contact pads of the second integrated circuit chip and PCB. The apparatus is operative for processing image signals generated by the WLC for attempting to decode the bar code symbol.

Package-on-package based integrated circuit chip imager

A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Fan-out semiconductor package

A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias.

Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device

A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.

Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die

A semiconductor package includes a leadframe A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion The top portion forms a top terminal lead structure A second lead finger is electrically connected to the first lead finger A portion of the second lead finger forms a bottom terminal lead structure A portion of the second lead finger corresponds to a bottom surface of the semiconductor package A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package

Leadframe Design for QFN Package with Top Terminal Leads

A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.

Henry Descalzo Bathan

Papers

Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device

Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die

Leadframe Design for QFN Package with Top Terminal Leads

Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die