A temperature compensated differential level shift circuit (Fig. 2). An ECL type buffered differential circuit employs a source of threshold voltage, VT (Fig. 3), which matches the temperature-dependent characteristic of the input section of the level shift circuit. In a preferred embodiment, s Schottky diode (52) is provided in the output section of a bandgap reference voltage generator (Fig. 3) which matches the temperature dependence of a Schottky diode (30) in the input section of the level shift circuit (Fig. 2). As temperature shifts, the threshold voltage will shift in a manner that tracks the temperature-produced shift in the input voltage as it passes through the Schottky diode in the input section of the level shift circuit. Matched PNP or NPN transistors (70, 72 and 71, 73 ) may also be used in the input section of the level shift circuit (Figs. 6A, 7A) and in the output section of the bandgap reference voltage generator (Figs. 6B, 7B).

Temperature compensated ttl to ecl translator

A plasma display panel for adaptively reducing load effect and improving luminescence efficiency and discharge efficiency, and a driving method thereof. A plasma display panel includes a capacitive load; a source capacitor; a sustain voltage source to generate a sustain voltage; a first inductor formed on a first current path where a current flows from the capacitive load to the source capacitor; a second inductor formed on a second current path where a current flows from the source capacitor to the capacitive load; a switch configuration and switch control circuit that controls the switching operations of the switch configuration such that at least two discharges may occur during one sustain pulse cycle.

Plasma display and driving method thereof

An ECL circuit comprising an output transistor having a high output voltage VOH guard band and a low output voltage VOL guard band with a temperature compensating network coupled to the output transistor for causing the high level output voltage VOH and low level output voltage VOL of the output transistor to remain within the maximum and minimum limits of the VOH and VOL guard bands over a wide temperature range.

Temperature compensation for ECL circuits

A temperature compensated bandgap voltage reference circuit employs an npn transistor based bypass circuit to maintain a constant collector current within the reference circuit. This bypass circuit draws a nominal current from the bandgap voltage reference circuit. The value of this current is set by a bias circuit responsive to changes in the supply voltage. As the supply voltage changes, the bias circuit varies the conductance of a bypass transistor to draw more or less current and thereby maintain the collector current within the reference circuit constant.

Bandgap voltage reference circuit with an NPN current bypass circuit

A first junction transistor, the emitter-to-base potential (V BE ) of which determines the negative-temperature-coefficient component of the standard voltage, is provided with direct-coupled collector-to-base feedback for adjusting its V BE to condition the transistor to conduct, as collector current, substantially all of an applied current that is temperature-independent or varies linearly with temperature. The positive-temperature-coefficient component of the standard voltage is developed as the difference between the offset potentials of a pair of semiconductor junctions, one of which may be the base-emitter junction of the first transistor. The negative- and positive-temperature-coefficient potentials are linearly combined to provide the standard voltage.

Voltage standard based on semiconductor junction offset potentials

An improved CML (Current Mode Logic) gate having voltage and temperature compensating means for maintaining output levels and input thresholds invariant with fluctations in supply voltage and junction temperature. The output of the compensating means, measured with respect to ground, will track variations in supply voltage on a one-to-one basis except that the output is allowed to vary by one Vbe with junction temperature. This output is supplied to the base of the constant-current source transistor which feeds the differential amplifier stage of the CML gate and to the base of a constant current source transistor whose collector is coupled to the base of the non-input transistor of the differential amplifier stage of the CML gate. The compensating circuitry includes an output transistor, resistive means for tracking variations in supply voltage, and a temperature compensation network having a temperature compensation factor of zero, both said resistive means and the output of said temperature compensation network are coupled to the base of the output transistor. The temperature compensation network achieves an overall compensation factor of zero by combining a temperature compensating subcircuit having a compensation factor of minus one with a temperature compensating subcircuit having a compensation factor of plus one via a unique voltage divider arrangement.

Herbert Stopper

Papers

Voltage and temperature compensation circuitry for current mode logic