Methods of selectively inhibiting deposition of silicon-containing films deposited by atomic layer deposition are provided. Selective inhibition involves exposure of an adsorbed layer of a silicon-containing precursor to a hydrogen-containing inhibitor, and in some instances, prior to exposure of the adsorbed layer to a second reactant. Exposure to a hydrogen-containing inhibitor may be performed with a plasma, and methods are suitable for selective inhibition in thermal or plasma enhanced atomic layer deposition of silicon-containing films.

Selective inhibition in atomic layer deposition of silicon-containing films

A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Semiconductor Device and Method of Fabricating the Same

Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

Capped ald films for doping fin-shaped channel regions of 3-d ic transistors

Methods and apparatuses for depositing films in high aspect ratio features and trenches using a post-dose treatment operation during atomic layer deposition are provided. Post-dose treatment operations are performed after adsorbing precursors onto the substrate to remove adsorbed precursors at the tops of features prior to converting the adsorbed precursors to a silicon-containing film. Post-dose treatments include exposure to non-oxidizing gas, exposure to non-oxidizing plasma, and exposure to ultraviolet radiation.

Selective atomic layer deposition with post-dose treatment

An embodiment of a Geiger-mode avalanche photodiode includes a body of semiconductor material having a first conductivity type, a first surface and a second surface; a trench extending through the body from the first surface and surrounding an active region; a lateral-isolation region within the trench, formed by a conductive region and an insulating region of dielectric material, the insulating region surrounding the conductive region; an anode region having a second conductivity type, extending within the active region and facing the first surface. The active region forms a cathode region extending between the anode region and the second surface, and defines a quenching resistor. The photodiode has a contact region of conductive material, overlying the first surface and in contact with the conductive region for connection thereof to a circuit biasing the conductive region, thereby a depletion region is formed in the active region around the insulating region.

Geiger-mode photodiode with integrated and adjustable quenching resistor, photodiode array, and manufacturing method thereof

A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

Medium voltage MOSFET device

A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Multiple shielding trench gate fet

A semiconductor device (100) contains a vertical MOS transistor (106) with instances of a vertical reduced surface field (RESURF) trench (112) on opposite sides of a vertical drift region (110). The vertical RESURF trench (112) contains a dielectric trench liner (114) on sidewalls, a lower field plate (120) and an upper field plate (122). The dielectric trench liner (114) between the lower field plate and the vertical drift region (110) is thicker than between the upper field plate and the vertical drift region (110). A gate (126) is disposed over the vertical drift region (110) and is separate from the upper field plate (122). The upper field plate (122) and the lower field plate (120) are electrically coupled to a source electrode of the vertical MOS transistor.

Dual resurf trench field plate in vertical mosfet

The object of this invention is to provide a method of manufacturing diodes, said method being a method of manufacturing semiconductor devices whereby an insulating film as the upper layer of the diode can be removed without causing film peeling or leakage. A photodiode is formed by forming a semiconductor layer of a second conduction type 12 upon the surface layer of a semiconductor layer of a first conduction type 11 , and next forming a removable mask layer 30 which has etching selectivity with respect to the semiconductor layer of a second conduction type, or alternately, forming an anti-reflection film AR upon the top layer of the semiconductor layer of a second conduction type and then forming a removable mask layer which has etching selectivity with respect to the anti-reflection film. Next, a removable insulating layer I which has etching selectivity with respect to the mask layer is formed upon the top layer of the mask layer. Next, a hole H with its bottom surface consisting solely of the top surface of the mask layer is formed in the insulating layer by using the mask layer as the etching stopper, and next, the mask layer is removed in areas exposed within the interior of the hole selectively with respect to the semiconductor layer of a second conduction type or anti-reflection film and the insulating film.

Method of manufacturing photodiodes

Current density in an insulated gate bipolar transistor (L-IGBT) may be increased by adding a second gate, and the corresponding MOS transistors, to the source area, which increases the base current compared to a L-IGBT with a single MOS gate. The current density may be further increased by extending the base of the bipolar transistor in the L-IGBT vertically to the bottom surface of the silicon on insulator (SOI) film in which the L-IGBT is fabricated. Adding a buffer diffused region around the sinks in the source improves the base current spatial uniformity, which improves the safe operating area (SOA) of the L-IGBT. A L-IGBT of either polarity may be formed with the inventive configurations. A method of forming the inventive L-IGBT is also disclosed.

Hideaki Kawahara

Papers

Medium voltage MOSFET device

Multiple shielding trench gate fet

Dual resurf trench field plate in vertical mosfet

Method of manufacturing photodiodes

Lateral insulated gate bipolar transistor