In a communication system, a first and a second master unit and at least one slave unit are interconnected via a twin conductor structure, the second master unit having a master coupling device which is connected between a control unit, a receiver unit and a transmitter unit to separate on the twin conductor structure the control unit from the receiver unit and the transmitter unit in a first mode of operation when data signals of the first master unit are received and to connect on the twin conductor structure the control unit to the receiver unit and the transmitter unit in the second mode of operation when the reception of data signals of the first master unit is interrupted, thereby carrying out a data transmission on the twin conductor structure.

Communication system having a master/slave structure

In a network, such as a large telecommunication switch, intended for the processing of information in different stations and for transmitting information between the stations, circuits (1) are provided which generate independently composite clock signals (CLSY-A, CLSY-B, CLSY-C) containing both a clocking rate (CLock) and a frame synchronizing rate (SYnch). These clock signals are transmitted on three different transmission lines in parallel and independently to a station (II), where some kind of information processing (4) is made in redundant planes (A, B, C). In the station (II) all incoming clock signals are fed to each one of three independently operating selector units (3) in which a choice of a clock signal is made for obtaining a clock signal to be used in the three redundant planes (A, B, C), arranged in parallel to each other and operating independently of each other, in the station.

Operation and maintenance of clock distribution networks having redundancy

In a network, such as a large telecommunication switch, intended for the processing of information in different stations and for transmitting information between the stations, centrally located circuits are provided, which independently generate clock signals (CLSY-A, CLSY-B, CLSY-C) containing both a system clock rate and a frame synchronizing rate. These clock signals are transmitted on several, in the preferred case three, different transmission lines to a station, where a multiplexer (63) makes a selection of a clock signal as controlled by evaluation circuits containing circuits (9, 11) for determining errors in the received clock signals and also containing a state machine (69). The multiplexer (63) selects periodically and repeatedly all the time a new clock signal in a cyclical pattern, which is accomplished by temporary, very short errors that are introduced when generating the issued clock signals. Thereby certainly all the time small phase jumps are introduced in the selected clock signal but at the same time the magnitude is reduced of a phase jump in relation to the former average phase position of the selected clock signal when possibly one of the incoming clock signals cannot be selected any more.

Clock selector system

PURPOSE:To prevent the adverse influence caused by troubles in a triplex system by providing a correction part, which reproduces a clock waveform having a certain width with the aid of an edge of an output waveform obtained by majority decision and outputs it, on an output of a clock synchronizing circuit of each system. CONSTITUTION:Respective systems A-C comprising a triplex system have clock synchronizing parts Sa-Sc with the same constitution, which are impressed by original clocks ocp1-ocp3 from a clock generator circuit provided on respective systems, synchronize clocks and output majority decision clocks mjcp1-mjcp3 of the same frequency. The clock synchronizing part Sa divides original clocks of its own system by a frequency dividing counter 1 and decides its output dcp1 and inputs dcp2 and dcp3 from other systems by majority in a majority decision circuit 2. Said part Sa compares the order of its output mjcp1 with that of the output of the counter 1 and judges whichever that its own system is any one of an advancing system, intermediate one and delay one. According to the result, the counter 1 is controlled by a control circuit 3, and a correction part Ca generates an output ccp with a certain width from the output mjcp1.

Clock pulse synchronizer in triple system

PURPOSE: To use a general bus type transmission control LSI by constituting an optical cable in a loop of dual systems and cutting off the loop by a master system of a master transmitter. CONSTITUTION: A transmission controller 2 is connected to two optical cable lines (A and B) different in transmission direction through a transmission line switch 3 and an photoelectric/electrooptic conversion part OE/EO. The transmission switch 3 is provided with switches SW which are controlled to transfer the reception input downstream or not, and these switches SW are switched by the indication from the external or said logic part. A redundant constitution is given to an R master transmitter in the transmission controller 2, and only the master system turns on the switch 3 to cut off down transfer. Consequently, a bus type constitution with the master transmitter of the master system as the terminal is adopted though the transmission line is constituted as a loop. When the master transmitter of the master system is switched to a slave system or is faulty, it is turned off and reception data is transferred downstream as it is. COPYRIGHT: (C)1989,JPO&Japio

Method for constituting optical dual system lan with high reliability

PURPOSE:To repeat an alternating operation even when the judging output of the same pattern is issued for a long time and to set a dealternating state when noncoincidence is obtained between data by inserting a frequency stabilizer between a bit data comparator and an FF circuit CONSTITUTION:The FF circuits FF1 and FF2 repeat the alternating operations as far as (0) is outputted from the output side X and (1) from the side Y of the bit data comparator 1 successively An AC wave outputted from the FF1 is rectified to a DC wave at a rectifier 31, and maintains the operation of a relay 32 Meanwhile, when noncoincidence information ie, (0), (0) or (1), (1) are outputted from the sides X and Y, they are surely detected by a frequency stabilization circuit In such a case, assuming that the output side Q01 of the FF1 is set at (1) and the output side Q11 of the FF2 at (0), (0) is outputted from the OR circuit of the frequency stabilization circuit 2, respectively Therefore, a pendulum circuit 3 can maintain the de-alternating state hereafter

Hideo Nakamura

Papers

Clock pulse synchronizer in triple system

Method for constituting optical dual system lan with high reliability

Method and device for stabilizing frequency of bit data comparing and judging device