H
Hirobumi Yokosuka
Researcher at Hitachi
Publications - 8
Citations - 317
Hirobumi Yokosuka is an academic researcher from Hitachi. The author has contributed to research in topics: Signal & Display device. The author has an hindex of 5, co-authored 8 publications receiving 317 citations.
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Patent
Small-sized information processor capable of scrolling screen in accordance with tilt, and scrolling method therefor
TL;DR: In this article, a small-sized information processor which is used while being held in one hand, and which can scroll a display screen in accordance with a tilt sensor is described, and the processing unit scrolls the display screen of the display unit on the basis of the calculated relative tilt angle.
Patent
Compact information processor
TL;DR: In this paper, the authors propose a compact information processor which enables an operator to scroll a screen without using his hand in which the compact information processors are not held at the time of using the Compact Information Processor in his other hand.
Patent
Electric washer system
Toyonori Horiuchi,Atsushi Hosokawa,Junichi Makioka,Yasushi Shinko,Kazufumi Takagishi,Hirobumi Yokosuka,靖 信耕,豊記 堀内,博文 横須賀,淳一 牧岡,敦志 細川,一史 高岸 +11 more
TL;DR: In this article, a washer operation program and equipment specifications are obtained from an electric washer 100 by a mobile telephone 200, and registered on a home page 410 on the Internet 400 by a short distance wireless communication, and a new washing and dehydration control program and reference information are obtained and provided to the electric washing and deodorization control program.
Patent
Display control system for a scan type display apparatus
TL;DR: In this article, a dual port memory having a random access port and a serial access port is used as a display memory and display data is inputted through the random access ports and outputting through the serial access ports.
Patent
Parallel-to-serial signal converting apparatus and image displaying system using the same
Hirobumi Yokosuka,Sakai Yasuo +1 more
TL;DR: In this paper, a parallel-to-serial signal-converting apparatus is described, which consists of a logic circuit for converting first parallel bit signals of a low frequency to be converted to a high frequency serial bit signal into second parallel bit signal having the same frequency as the first bit signals and having information as to whether adjacent two bits of the serial bit signals are equal in level or not.