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Hiromasa Yamamoto

Researcher at Panasonic

Publications -  16
Citations -  169

Hiromasa Yamamoto is an academic researcher from Panasonic. The author has contributed to research in topics: Electromagnetic coil & Inductance. The author has an hindex of 8, co-authored 16 publications receiving 169 citations.

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Patent

Method of manufacturing a chip coil

TL;DR: In this paper, a method of manufacturing a chip coil, including a magnetic core, a winding wire, and internal terminal electrodes, a fired mass of magnetic material surrounding and encapsulating the coil element, and external terminal electrodes electrically connected to the internal terminals, is presented.
Patent

Manufacture of inductor

TL;DR: In this paper, a method for obtaining an inductor with a simple process, good mass productivity, easy adjustment of inductance and a few occurrence of trouble at the timing of dipping solder by a method wherein a long winding inductor bar coated a magnetic substance on the circumference of the bar is cut.
Patent

Manufacture of chip inductor

TL;DR: In this paper, the authors proposed a method to simplify a manufacturing process by stacking up slitted green sheets of magnetic material by a method wherein a slit is provided in every coil-forming pattern at a part where electroconductive patterns are to overlap for connection via the slit and another part is arranged to meet a corresponding part in the upper layer.
Patent

Inductance part and its manufacturing method

TL;DR: In this article, the inductance part comprises a pillar-like base (21) made of a magnetic material, a conductor layer (24) covering the end and side faces of the base, a coil portion (27) having grooves, and linear conductors formed in/on the conductor layer covering the side faces, electrode portions (28) composed of the conductor layers covering end faces, and a magnetic body portion (31) made by a sintered magnetic body and provided over the coil portion.
Patent

Method of manufacturing chip inductor

TL;DR: In this paper, a method of manufacturing a chip inductor, comprising the conductive layer forming step of forming a conductive layers (4) on the outer peripheral surfaces (2) and end surfaces (3) of a substrate, is presented.